// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_epf_cfgspace_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:13 Create file
// ******************************************************************************

#ifndef __HIPCIEC_EPF_CFGSPACE_REG_OFFSET_FIELD_H__
#define __HIPCIEC_EPF_CFGSPACE_REG_OFFSET_FIELD_H__

#define HIPCIEC_EPF_CFGSPACE_DEVICE_ID_LEN    16
#define HIPCIEC_EPF_CFGSPACE_DEVICE_ID_OFFSET 16
#define HIPCIEC_EPF_CFGSPACE_VENDOR_ID_LEN    16
#define HIPCIEC_EPF_CFGSPACE_VENDOR_ID_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_CFG_DELETE_PAR_ERR_LEN      1
#define HIPCIEC_EPF_CFGSPACE_CFG_DELETE_PAR_ERR_OFFSET   31
#define HIPCIEC_EPF_CFGSPACE_CFG_RX_SYS_ERR_LEN          1
#define HIPCIEC_EPF_CFGSPACE_CFG_RX_SYS_ERR_OFFSET       30
#define HIPCIEC_EPF_CFGSPACE_CFG_RX_MASTER_ABORT_LEN     1
#define HIPCIEC_EPF_CFGSPACE_CFG_RX_MASTER_ABORT_OFFSET  29
#define HIPCIEC_EPF_CFGSPACE_CFG_RX_TARGET_ABORT_LEN     1
#define HIPCIEC_EPF_CFGSPACE_CFG_RX_TARGET_ABORT_OFFSET  28
#define HIPCIEC_EPF_CFGSPACE_CFG_SIG_TARGET_ABORT_LEN    1
#define HIPCIEC_EPF_CFGSPACE_CFG_SIG_TARGET_ABORT_OFFSET 27
#define HIPCIEC_EPF_CFGSPACE_CFG_DEVSEL_TIMING_LEN       2
#define HIPCIEC_EPF_CFGSPACE_CFG_DEVSEL_TIMING_OFFSET    25
#define HIPCIEC_EPF_CFGSPACE_CFG_MDATA_PAR_ERR_LEN       1
#define HIPCIEC_EPF_CFGSPACE_CFG_MDATA_PAR_ERR_OFFSET    24
#define HIPCIEC_EPF_CFGSPACE_CFG_FASTB2B_CAP_LEN         1
#define HIPCIEC_EPF_CFGSPACE_CFG_FASTB2B_CAP_OFFSET      23
#define HIPCIEC_EPF_CFGSPACE_CFG_66MHZ_CAP_LEN           1
#define HIPCIEC_EPF_CFGSPACE_CFG_66MHZ_CAP_OFFSET        21
#define HIPCIEC_EPF_CFGSPACE_CFG_CAP_LIST_LEN            1
#define HIPCIEC_EPF_CFGSPACE_CFG_CAP_LIST_OFFSET         20
#define HIPCIEC_EPF_CFGSPACE_CFG_INTX_STATUS_LEN         1
#define HIPCIEC_EPF_CFGSPACE_CFG_INTX_STATUS_OFFSET      19
#define HIPCIEC_EPF_CFGSPACE_IMMEDIATE_READINESS_LEN     1
#define HIPCIEC_EPF_CFGSPACE_IMMEDIATE_READINESS_OFFSET  16
#define HIPCIEC_EPF_CFGSPACE_CFG_INTX_DISABLE_LEN        1
#define HIPCIEC_EPF_CFGSPACE_CFG_INTX_DISABLE_OFFSET     10
#define HIPCIEC_EPF_CFGSPACE_CFG_FAST_B2B_EN_LEN         1
#define HIPCIEC_EPF_CFGSPACE_CFG_FAST_B2B_EN_OFFSET      9
#define HIPCIEC_EPF_CFGSPACE_CFG_SERR_EN_LEN             1
#define HIPCIEC_EPF_CFGSPACE_CFG_SERR_EN_OFFSET          8
#define HIPCIEC_EPF_CFGSPACE_IDSEL_STEPPING_LEN          1
#define HIPCIEC_EPF_CFGSPACE_IDSEL_STEPPING_OFFSET       7
#define HIPCIEC_EPF_CFGSPACE_CFG_PARITY_ERR_RESP_LEN     1
#define HIPCIEC_EPF_CFGSPACE_CFG_PARITY_ERR_RESP_OFFSET  6
#define HIPCIEC_EPF_CFGSPACE_CFG_VGA_SNOOP_EN_LEN        1
#define HIPCIEC_EPF_CFGSPACE_CFG_VGA_SNOOP_EN_OFFSET     5
#define HIPCIEC_EPF_CFGSPACE_CFG_MEM_WR_INVLD_EN_LEN     1
#define HIPCIEC_EPF_CFGSPACE_CFG_MEM_WR_INVLD_EN_OFFSET  4
#define HIPCIEC_EPF_CFGSPACE_CFG_SPECIAL_CYCLE_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_CFG_SPECIAL_CYCLE_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_CFG_MASTER_EN_LEN           1
#define HIPCIEC_EPF_CFGSPACE_CFG_MASTER_EN_OFFSET        2
#define HIPCIEC_EPF_CFGSPACE_CFG_MEM_SPACE_EN_LEN        1
#define HIPCIEC_EPF_CFGSPACE_CFG_MEM_SPACE_EN_OFFSET     1
#define HIPCIEC_EPF_CFGSPACE_CFG_IO_SPACE_EN_LEN         1
#define HIPCIEC_EPF_CFGSPACE_CFG_IO_SPACE_EN_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_BASE_CLASS_CODE_LEN    8
#define HIPCIEC_EPF_CFGSPACE_BASE_CLASS_CODE_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_SUB_CLASS_CODE_LEN     8
#define HIPCIEC_EPF_CFGSPACE_SUB_CLASS_CODE_OFFSET  16
#define HIPCIEC_EPF_CFGSPACE_PROGRAM_INF_LEN        8
#define HIPCIEC_EPF_CFGSPACE_PROGRAM_INF_OFFSET     8
#define HIPCIEC_EPF_CFGSPACE_REVISION_ID_LEN        8
#define HIPCIEC_EPF_CFGSPACE_REVISION_ID_OFFSET     0

#define HIPCIEC_EPF_CFGSPACE_BIST_CAP_LEN             1
#define HIPCIEC_EPF_CFGSPACE_BIST_CAP_OFFSET          31
#define HIPCIEC_EPF_CFGSPACE_START_BIST_LEN           1
#define HIPCIEC_EPF_CFGSPACE_START_BIST_OFFSET        30
#define HIPCIEC_EPF_CFGSPACE_BIST_RESULT_LEN          4
#define HIPCIEC_EPF_CFGSPACE_BIST_RESULT_OFFSET       24
#define HIPCIEC_EPF_CFGSPACE_MULTI_FUNC_DEIVCE_LEN    1
#define HIPCIEC_EPF_CFGSPACE_MULTI_FUNC_DEIVCE_OFFSET 23
#define HIPCIEC_EPF_CFGSPACE_CFG_HEADER_TYPE_LEN      7
#define HIPCIEC_EPF_CFGSPACE_CFG_HEADER_TYPE_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_CFG_LATENCY_TIMER_LEN    8
#define HIPCIEC_EPF_CFGSPACE_CFG_LATENCY_TIMER_OFFSET 8
#define HIPCIEC_EPF_CFGSPACE_CFG_CACHLIE_SIZE_LEN     8
#define HIPCIEC_EPF_CFGSPACE_CFG_CACHLIE_SIZE_OFFSET  0

#define HIPCIEC_EPF_CFGSPACE_CFG_BAR0_ADDR_LEN           28
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR0_ADDR_OFFSET        4
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR0_PREFETCH_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR0_PREFETCH_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR0_WIDTH_LEN          1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR0_WIDTH_OFFSET       2
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR0_TYPE_LEN           1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR0_TYPE_OFFSET        0

#define HIPCIEC_EPF_CFGSPACE_CFG_BAR1_ADDR_LEN           28
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR1_ADDR_OFFSET        4
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR1_PREFETCH_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR1_PREFETCH_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR1_WIDTH_LEN          2
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR1_WIDTH_OFFSET       1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR1_TYPE_LEN           1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR1_TYPE_OFFSET        0

#define HIPCIEC_EPF_CFGSPACE_CFG_BAR2_ADDR_LEN           28
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR2_ADDR_OFFSET        4
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR2_PREFETCH_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR2_PREFETCH_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR2_WIDTH_LEN          1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR2_WIDTH_OFFSET       2
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR2_TYPE_LEN           1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR2_TYPE_OFFSET        0

#define HIPCIEC_EPF_CFGSPACE_CFG_BAR3_ADDR_LEN           28
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR3_ADDR_OFFSET        4
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR3_PREFETCH_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR3_PREFETCH_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR3_WIDTH_LEN          2
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR3_WIDTH_OFFSET       1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR3_TYPE_LEN           1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR3_TYPE_OFFSET        0

#define HIPCIEC_EPF_CFGSPACE_CFG_BAR4_ADDR_LEN           28
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR4_ADDR_OFFSET        4
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR4_PREFETCH_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR4_PREFETCH_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR4_WIDTH_LEN          1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR4_WIDTH_OFFSET       2
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR4_TYPE_LEN           1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR4_TYPE_OFFSET        0

#define HIPCIEC_EPF_CFGSPACE_CFG_BAR5_ADDR_LEN           28
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR5_ADDR_OFFSET        4
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR5_PREFETCH_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR5_PREFETCH_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR5_WIDTH_LEN          2
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR5_WIDTH_OFFSET       1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR5_TYPE_LEN           1
#define HIPCIEC_EPF_CFGSPACE_CFG_BAR5_TYPE_OFFSET        0

#define HIPCIEC_EPF_CFGSPACE_CARBUS_CIS_PTR_LEN    32
#define HIPCIEC_EPF_CFGSPACE_CARBUS_CIS_PTR_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_CFG_SUB_SYS_ID_LEN       16
#define HIPCIEC_EPF_CFGSPACE_CFG_SUB_SYS_ID_OFFSET    16
#define HIPCIEC_EPF_CFGSPACE_CFG_SYS_VENDOR_ID_LEN    16
#define HIPCIEC_EPF_CFGSPACE_CFG_SYS_VENDOR_ID_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_EXT_ROM_BASE_ADDR_LEN    21
#define HIPCIEC_EPF_CFGSPACE_EXT_ROM_BASE_ADDR_OFFSET 11
#define HIPCIEC_EPF_CFGSPACE_EXT_ROM_ENABLE_LEN       1
#define HIPCIEC_EPF_CFGSPACE_EXT_ROM_ENABLE_OFFSET    0

#define HIPCIEC_EPF_CFGSPACE_CFG_CAP_PTR_LEN    8
#define HIPCIEC_EPF_CFGSPACE_CFG_CAP_PTR_OFFSET 0



#define HIPCIEC_EPF_CFGSPACE_CFG_MAX_LAT_LEN     8
#define HIPCIEC_EPF_CFGSPACE_CFG_MAX_LAT_OFFSET  24
#define HIPCIEC_EPF_CFGSPACE_CFG_MIN_GNT_LEN     8
#define HIPCIEC_EPF_CFGSPACE_CFG_MIN_GNT_OFFSET  16
#define HIPCIEC_EPF_CFGSPACE_CFG_INT_PIN_LEN     8
#define HIPCIEC_EPF_CFGSPACE_CFG_INT_PIN_OFFSET  8
#define HIPCIEC_EPF_CFGSPACE_CFG_INT_LINE_LEN    8
#define HIPCIEC_EPF_CFGSPACE_CFG_INT_LINE_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_UNDEFINE_00_LEN           1
#define HIPCIEC_EPF_CFGSPACE_UNDEFINE_00_OFFSET        30
#define HIPCIEC_EPF_CFGSPACE_INT_MSG_NUM_LEN           5
#define HIPCIEC_EPF_CFGSPACE_INT_MSG_NUM_OFFSET        25
#define HIPCIEC_EPF_CFGSPACE_SLOT_IMPLEMENT_LEN        1
#define HIPCIEC_EPF_CFGSPACE_SLOT_IMPLEMENT_OFFSET     24
#define HIPCIEC_EPF_CFGSPACE_PORT_TYPE_LEN             4
#define HIPCIEC_EPF_CFGSPACE_PORT_TYPE_OFFSET          20
#define HIPCIEC_EPF_CFGSPACE_PCI_CAP_VER_LEN           4
#define HIPCIEC_EPF_CFGSPACE_PCI_CAP_VER_OFFSET        16
#define HIPCIEC_EPF_CFGSPACE_PCIE_NEXT_CAP_ADDR_LEN    8
#define HIPCIEC_EPF_CFGSPACE_PCIE_NEXT_CAP_ADDR_OFFSET 8
#define HIPCIEC_EPF_CFGSPACE_PCI_CAPID_LEN             8
#define HIPCIEC_EPF_CFGSPACE_PCI_CAPID_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_FLR_CAP_LEN                     1
#define HIPCIEC_EPF_CFGSPACE_FLR_CAP_OFFSET                  28
#define HIPCIEC_EPF_CFGSPACE_CAP_SLOT_PWR_SCA_LEN            2
#define HIPCIEC_EPF_CFGSPACE_CAP_SLOT_PWR_SCA_OFFSET         26
#define HIPCIEC_EPF_CFGSPACE_CAP_SLOT_PWR_LIMIT_VAL_LEN      8
#define HIPCIEC_EPF_CFGSPACE_CAP_SLOT_PWR_LIMIT_VAL_OFFSET   18
#define HIPCIEC_EPF_CFGSPACE_RO_BASE_ERR_RPT_LEN             1
#define HIPCIEC_EPF_CFGSPACE_RO_BASE_ERR_RPT_OFFSET          15
#define HIPCIEC_EPF_CFGSPACE_UNDEFINE_04_LEN                 3
#define HIPCIEC_EPF_CFGSPACE_UNDEFINE_04_OFFSET              12
#define HIPCIEC_EPF_CFGSPACE_EP_L1_ACCEPT_LAT_LEN            3
#define HIPCIEC_EPF_CFGSPACE_EP_L1_ACCEPT_LAT_OFFSET         9
#define HIPCIEC_EPF_CFGSPACE_EP_L0S_ACCEPT_LAT_LEN           3
#define HIPCIEC_EPF_CFGSPACE_EP_L0S_ACCEPT_LAT_OFFSET        6
#define HIPCIEC_EPF_CFGSPACE_EXT_TAG_SUP_LEN                 1
#define HIPCIEC_EPF_CFGSPACE_EXT_TAG_SUP_OFFSET              5
#define HIPCIEC_EPF_CFGSPACE_PHANTOM_FUN_SUP_LEN             2
#define HIPCIEC_EPF_CFGSPACE_PHANTOM_FUN_SUP_OFFSET          3
#define HIPCIEC_EPF_CFGSPACE_MAX_PAYLOAD_SIZE_SUPPORT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_MAX_PAYLOAD_SIZE_SUPPORT_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_EMERGENCY_PWR_REDUCE_DET_LEN    1
#define HIPCIEC_EPF_CFGSPACE_EMERGENCY_PWR_REDUCE_DET_OFFSET 22
#define HIPCIEC_EPF_CFGSPACE_TLP_PENDING_LEN                 1
#define HIPCIEC_EPF_CFGSPACE_TLP_PENDING_OFFSET              21
#define HIPCIEC_EPF_CFGSPACE_AUX_PWR_DETECT_LEN              1
#define HIPCIEC_EPF_CFGSPACE_AUX_PWR_DETECT_OFFSET           20
#define HIPCIEC_EPF_CFGSPACE_UR_DETECT_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_UR_DETECT_OFFSET                19
#define HIPCIEC_EPF_CFGSPACE_FAT_ERR_DETECT_LEN              1
#define HIPCIEC_EPF_CFGSPACE_FAT_ERR_DETECT_OFFSET           18
#define HIPCIEC_EPF_CFGSPACE_NON_FATA_DETECT_LEN             1
#define HIPCIEC_EPF_CFGSPACE_NON_FATA_DETECT_OFFSET          17
#define HIPCIEC_EPF_CFGSPACE_COR_ERR_DETECT_LEN              1
#define HIPCIEC_EPF_CFGSPACE_COR_ERR_DETECT_OFFSET           16
#define HIPCIEC_EPF_CFGSPACE_INIT_FLR_RESET_LEN              1
#define HIPCIEC_EPF_CFGSPACE_INIT_FLR_RESET_OFFSET           15
#define HIPCIEC_EPF_CFGSPACE_MAX_READ_REQ_SIZE_LEN           3
#define HIPCIEC_EPF_CFGSPACE_MAX_READ_REQ_SIZE_OFFSET        12
#define HIPCIEC_EPF_CFGSPACE_NO_SNOOP_EN_LEN                 1
#define HIPCIEC_EPF_CFGSPACE_NO_SNOOP_EN_OFFSET              11
#define HIPCIEC_EPF_CFGSPACE_AUX_PWR_PM_EN_LEN               1
#define HIPCIEC_EPF_CFGSPACE_AUX_PWR_PM_EN_OFFSET            10
#define HIPCIEC_EPF_CFGSPACE_PHANTOM_FUNC_EN_LEN             1
#define HIPCIEC_EPF_CFGSPACE_PHANTOM_FUNC_EN_OFFSET          9
#define HIPCIEC_EPF_CFGSPACE_EXTEND_TAG_EN_LEN               1
#define HIPCIEC_EPF_CFGSPACE_EXTEND_TAG_EN_OFFSET            8
#define HIPCIEC_EPF_CFGSPACE_MAX_PAYLOAD_SIZE_LEN            3
#define HIPCIEC_EPF_CFGSPACE_MAX_PAYLOAD_SIZE_OFFSET         5
#define HIPCIEC_EPF_CFGSPACE_RELAX_ORDER_EN_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RELAX_ORDER_EN_OFFSET           4
#define HIPCIEC_EPF_CFGSPACE_UR_RPT_EN_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_UR_RPT_EN_OFFSET                3
#define HIPCIEC_EPF_CFGSPACE_FAT_ERR_RPT_EN_LEN              1
#define HIPCIEC_EPF_CFGSPACE_FAT_ERR_RPT_EN_OFFSET           2
#define HIPCIEC_EPF_CFGSPACE_NON_FAT_RPT_EN_LEN              1
#define HIPCIEC_EPF_CFGSPACE_NON_FAT_RPT_EN_OFFSET           1
#define HIPCIEC_EPF_CFGSPACE_COR_ERR_RPT_EN_LEN              1
#define HIPCIEC_EPF_CFGSPACE_COR_ERR_RPT_EN_OFFSET           0

#define HIPCIEC_EPF_CFGSPACE_PORT_NUM_LEN                   8
#define HIPCIEC_EPF_CFGSPACE_PORT_NUM_OFFSET                24
#define HIPCIEC_EPF_CFGSPACE_ASPM_OPT_COMPLIANCE_LEN        1
#define HIPCIEC_EPF_CFGSPACE_ASPM_OPT_COMPLIANCE_OFFSET     22
#define HIPCIEC_EPF_CFGSPACE_LINK_BAND_NOTICE_CAP_LEN       1
#define HIPCIEC_EPF_CFGSPACE_LINK_BAND_NOTICE_CAP_OFFSET    21
#define HIPCIEC_EPF_CFGSPACE_DL_LINK_ACT_RPT_CAP_LEN        1
#define HIPCIEC_EPF_CFGSPACE_DL_LINK_ACT_RPT_CAP_OFFSET     20
#define HIPCIEC_EPF_CFGSPACE_SURPRISE_DN_ERR_RPT_CAP_LEN    1
#define HIPCIEC_EPF_CFGSPACE_SURPRISE_DN_ERR_RPT_CAP_OFFSET 19
#define HIPCIEC_EPF_CFGSPACE_CLOCK_PM_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_CLOCK_PM_OFFSET                18
#define HIPCIEC_EPF_CFGSPACE_L1_EXIT_LAT_LEN                3
#define HIPCIEC_EPF_CFGSPACE_L1_EXIT_LAT_OFFSET             15
#define HIPCIEC_EPF_CFGSPACE_L0_EXIT_LAT_LEN                3
#define HIPCIEC_EPF_CFGSPACE_L0_EXIT_LAT_OFFSET             12
#define HIPCIEC_EPF_CFGSPACE_ASPM_SUP_LEN                   2
#define HIPCIEC_EPF_CFGSPACE_ASPM_SUP_OFFSET                10
#define HIPCIEC_EPF_CFGSPACE_MAX_LINK_WIDTH_LEN             6
#define HIPCIEC_EPF_CFGSPACE_MAX_LINK_WIDTH_OFFSET          4
#define HIPCIEC_EPF_CFGSPACE_MAX_LINK_SPEED_LEN             4
#define HIPCIEC_EPF_CFGSPACE_MAX_LINK_SPEED_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_LINK_AUTO_BAND_STATUS_LEN    1
#define HIPCIEC_EPF_CFGSPACE_LINK_AUTO_BAND_STATUS_OFFSET 31
#define HIPCIEC_EPF_CFGSPACE_LINK_BAND_STATUS_LEN         1
#define HIPCIEC_EPF_CFGSPACE_LINK_BAND_STATUS_OFFSET      30
#define HIPCIEC_EPF_CFGSPACE_DL_CFG_LINK_ACTIVE_LEN       1
#define HIPCIEC_EPF_CFGSPACE_DL_CFG_LINK_ACTIVE_OFFSET    29
#define HIPCIEC_EPF_CFGSPACE_SLOT_CLK_CFG_LEN             1
#define HIPCIEC_EPF_CFGSPACE_SLOT_CLK_CFG_OFFSET          28
#define HIPCIEC_EPF_CFGSPACE_LINK_TRAINING_LEN            1
#define HIPCIEC_EPF_CFGSPACE_LINK_TRAINING_OFFSET         27
#define HIPCIEC_EPF_CFGSPACE_UNDEFINED_12_LEN             1
#define HIPCIEC_EPF_CFGSPACE_UNDEFINED_12_OFFSET          26
#define HIPCIEC_EPF_CFGSPACE_MAC_CUR_LINK_WIDTH_LEN       6
#define HIPCIEC_EPF_CFGSPACE_MAC_CUR_LINK_WIDTH_OFFSET    20
#define HIPCIEC_EPF_CFGSPACE_MAC_CUR_LINK_SPEED_LEN       4
#define HIPCIEC_EPF_CFGSPACE_MAC_CUR_LINK_SPEED_OFFSET    16
#define HIPCIEC_EPF_CFGSPACE_DRS_SIGNAL_CTRL_LEN          2
#define HIPCIEC_EPF_CFGSPACE_DRS_SIGNAL_CTRL_OFFSET       14
#define HIPCIEC_EPF_CFGSPACE_LINK_AUTO_BAND_INT_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_LINK_AUTO_BAND_INT_EN_OFFSET 11
#define HIPCIEC_EPF_CFGSPACE_LINK_BAND_INT_EN_LEN         1
#define HIPCIEC_EPF_CFGSPACE_LINK_BAND_INT_EN_OFFSET      10
#define HIPCIEC_EPF_CFGSPACE_HW_AUTO_WIDTH_DIS_LEN        1
#define HIPCIEC_EPF_CFGSPACE_HW_AUTO_WIDTH_DIS_OFFSET     9
#define HIPCIEC_EPF_CFGSPACE_CLOCK_PM_EN_LEN              1
#define HIPCIEC_EPF_CFGSPACE_CLOCK_PM_EN_OFFSET           8
#define HIPCIEC_EPF_CFGSPACE_EXTENDED_SYNC_LEN            1
#define HIPCIEC_EPF_CFGSPACE_EXTENDED_SYNC_OFFSET         7
#define HIPCIEC_EPF_CFGSPACE_COMMON_CLK_CFG_LEN           1
#define HIPCIEC_EPF_CFGSPACE_COMMON_CLK_CFG_OFFSET        6
#define HIPCIEC_EPF_CFGSPACE_RETRAIN_LINK_LEN             1
#define HIPCIEC_EPF_CFGSPACE_RETRAIN_LINK_OFFSET          5
#define HIPCIEC_EPF_CFGSPACE_LINK_DISABLE_LEN             1
#define HIPCIEC_EPF_CFGSPACE_LINK_DISABLE_OFFSET          4
#define HIPCIEC_EPF_CFGSPACE_RCB_LEN                      1
#define HIPCIEC_EPF_CFGSPACE_RCB_OFFSET                   3
#define HIPCIEC_EPF_CFGSPACE_ASPM_CTRL_LEN                2
#define HIPCIEC_EPF_CFGSPACE_ASPM_CTRL_OFFSET             0

#define HIPCIEC_EPF_CFGSPACE_PHYSICAL_SLOT_NUM_LEN       13
#define HIPCIEC_EPF_CFGSPACE_PHYSICAL_SLOT_NUM_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_NO_COMMAN_CPLED_SUP_LEN     1
#define HIPCIEC_EPF_CFGSPACE_NO_COMMAN_CPLED_SUP_OFFSET  18
#define HIPCIEC_EPF_CFGSPACE_ELEC_INTERLOCK_PRE_LEN      1
#define HIPCIEC_EPF_CFGSPACE_ELEC_INTERLOCK_PRE_OFFSET   17
#define HIPCIEC_EPF_CFGSPACE_SLOT_PWR_LIMIT_SCALE_LEN    2
#define HIPCIEC_EPF_CFGSPACE_SLOT_PWR_LIMIT_SCALE_OFFSET 15
#define HIPCIEC_EPF_CFGSPACE_SLOT_PWR_LIMIT_VAL_LEN      8
#define HIPCIEC_EPF_CFGSPACE_SLOT_PWR_LIMIT_VAL_OFFSET   7
#define HIPCIEC_EPF_CFGSPACE_HOT_PLUG_CAP_LEN            1
#define HIPCIEC_EPF_CFGSPACE_HOT_PLUG_CAP_OFFSET         6
#define HIPCIEC_EPF_CFGSPACE_HOT_PLUG_SURPRISE_LEN       1
#define HIPCIEC_EPF_CFGSPACE_HOT_PLUG_SURPRISE_OFFSET    5
#define HIPCIEC_EPF_CFGSPACE_PWR_INDICATOR_PRE_LEN       1
#define HIPCIEC_EPF_CFGSPACE_PWR_INDICATOR_PRE_OFFSET    4
#define HIPCIEC_EPF_CFGSPACE_ATT_INDECATOR_PRE_LEN       1
#define HIPCIEC_EPF_CFGSPACE_ATT_INDECATOR_PRE_OFFSET    3
#define HIPCIEC_EPF_CFGSPACE_MSL_SENSOR_PRE_LEN          1
#define HIPCIEC_EPF_CFGSPACE_MSL_SENSOR_PRE_OFFSET       2
#define HIPCIEC_EPF_CFGSPACE_PWR_CTRL_PRE_LEN            1
#define HIPCIEC_EPF_CFGSPACE_PWR_CTRL_PRE_OFFSET         1
#define HIPCIEC_EPF_CFGSPACE_ATT_BUTTON_PRE_LEN          1
#define HIPCIEC_EPF_CFGSPACE_ATT_BUTTON_PRE_OFFSET       0

#define HIPCIEC_EPF_CFGSPACE_DL_STATE_CHANGE_LEN           1
#define HIPCIEC_EPF_CFGSPACE_DL_STATE_CHANGE_OFFSET        24
#define HIPCIEC_EPF_CFGSPACE_ELEC_INTERLOCK_ST_LEN         1
#define HIPCIEC_EPF_CFGSPACE_ELEC_INTERLOCK_ST_OFFSET      23
#define HIPCIEC_EPF_CFGSPACE_PRESENCD_DET_ST_LEN           1
#define HIPCIEC_EPF_CFGSPACE_PRESENCD_DET_ST_OFFSET        22
#define HIPCIEC_EPF_CFGSPACE_MRL_SENSOR_ST_LEN             1
#define HIPCIEC_EPF_CFGSPACE_MRL_SENSOR_ST_OFFSET          21
#define HIPCIEC_EPF_CFGSPACE_COMMAND_CPLED_LEN             1
#define HIPCIEC_EPF_CFGSPACE_COMMAND_CPLED_OFFSET          20
#define HIPCIEC_EPF_CFGSPACE_PRESENCD_DET_CHANGE_LEN       1
#define HIPCIEC_EPF_CFGSPACE_PRESENCD_DET_CHANGE_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_MRL_SENSOR_CHANGE_LEN         1
#define HIPCIEC_EPF_CFGSPACE_MRL_SENSOR_CHANGE_OFFSET      18
#define HIPCIEC_EPF_CFGSPACE_PWR_FAULT_DET_LEN             1
#define HIPCIEC_EPF_CFGSPACE_PWR_FAULT_DET_OFFSET          17
#define HIPCIEC_EPF_CFGSPACE_ATTENTION_BUTTON_LEN          1
#define HIPCIEC_EPF_CFGSPACE_ATTENTION_BUTTON_OFFSET       16
#define HIPCIEC_EPF_CFGSPACE_AUTO_SLOT_PLMT_DISABLE_LEN    1
#define HIPCIEC_EPF_CFGSPACE_AUTO_SLOT_PLMT_DISABLE_OFFSET 13
#define HIPCIEC_EPF_CFGSPACE_DL_STATE_CHANGE_EN_LEN        1
#define HIPCIEC_EPF_CFGSPACE_DL_STATE_CHANGE_EN_OFFSET     12
#define HIPCIEC_EPF_CFGSPACE_ELEC_INTERLOCK_CTRL_LEN       1
#define HIPCIEC_EPF_CFGSPACE_ELEC_INTERLOCK_CTRL_OFFSET    11
#define HIPCIEC_EPF_CFGSPACE_PWR_CTRLED_CTRL_LEN           1
#define HIPCIEC_EPF_CFGSPACE_PWR_CTRLED_CTRL_OFFSET        10
#define HIPCIEC_EPF_CFGSPACE_PWR_INDICATOR_CTRL_LEN        2
#define HIPCIEC_EPF_CFGSPACE_PWR_INDICATOR_CTRL_OFFSET     8
#define HIPCIEC_EPF_CFGSPACE_ATT_INDICATOR_CTRL_LEN        2
#define HIPCIEC_EPF_CFGSPACE_ATT_INDICATOR_CTRL_OFFSET     6
#define HIPCIEC_EPF_CFGSPACE_HOT_PLUG_INT_EN_LEN           1
#define HIPCIEC_EPF_CFGSPACE_HOT_PLUG_INT_EN_OFFSET        5
#define HIPCIEC_EPF_CFGSPACE_COMMAND_CPLED_INT_EN_LEN      1
#define HIPCIEC_EPF_CFGSPACE_COMMAND_CPLED_INT_EN_OFFSET   4
#define HIPCIEC_EPF_CFGSPACE_PRESENCE_DET_CHANGE_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_PRESENCE_DET_CHANGE_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_MRL_SENSOR_CHANGE_EN_LEN      1
#define HIPCIEC_EPF_CFGSPACE_MRL_SENSOR_CHANGE_EN_OFFSET   2
#define HIPCIEC_EPF_CFGSPACE_PWR_FAULT_DET_EN_LEN          1
#define HIPCIEC_EPF_CFGSPACE_PWR_FAULT_DET_EN_OFFSET       1
#define HIPCIEC_EPF_CFGSPACE_ATT_BUTTOM_PRE_EN_LEN         1
#define HIPCIEC_EPF_CFGSPACE_ATT_BUTTOM_PRE_EN_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_CRS_SW_VISIBILITY_LEN        1
#define HIPCIEC_EPF_CFGSPACE_CRS_SW_VISIBILITY_OFFSET     16
#define HIPCIEC_EPF_CFGSPACE_CRS_SW_VISIBILITY_EN_LEN     1
#define HIPCIEC_EPF_CFGSPACE_CRS_SW_VISIBILITY_EN_OFFSET  4
#define HIPCIEC_EPF_CFGSPACE_PME_INT_EN_LEN               1
#define HIPCIEC_EPF_CFGSPACE_PME_INT_EN_OFFSET            3
#define HIPCIEC_EPF_CFGSPACE_SYS_ERR_ON_FAT_ERR_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_SYS_ERR_ON_FAT_ERR_EN_OFFSET 2
#define HIPCIEC_EPF_CFGSPACE_SYS_ERR_ON_NON_FAT_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_SYS_ERR_ON_NON_FAT_EN_OFFSET 1
#define HIPCIEC_EPF_CFGSPACE_SYS_ERR_ON_COR_ERR_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_SYS_ERR_ON_COR_ERR_EN_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_PME_PENDING_LEN      1
#define HIPCIEC_EPF_CFGSPACE_PME_PENDING_OFFSET   17
#define HIPCIEC_EPF_CFGSPACE_PME_STATUS_RT_LEN    1
#define HIPCIEC_EPF_CFGSPACE_PME_STATUS_RT_OFFSET 16
#define HIPCIEC_EPF_CFGSPACE_PME_RID_LEN          16
#define HIPCIEC_EPF_CFGSPACE_PME_RID_OFFSET       0

#define HIPCIEC_EPF_CFGSPACE_FRS_SUP_LEN                          1
#define HIPCIEC_EPF_CFGSPACE_FRS_SUP_OFFSET                       31
#define HIPCIEC_EPF_CFGSPACE_EMERGENCY_PWR_REDUCE_INIT_REQ_LEN    1
#define HIPCIEC_EPF_CFGSPACE_EMERGENCY_PWR_REDUCE_INIT_REQ_OFFSET 26
#define HIPCIEC_EPF_CFGSPACE_EMERGENCY_PWR_REDUCE_SUP_LEN         2
#define HIPCIEC_EPF_CFGSPACE_EMERGENCY_PWR_REDUCE_SUP_OFFSET      24
#define HIPCIEC_EPF_CFGSPACE_MAX_END_END_PFX_LEN                  2
#define HIPCIEC_EPF_CFGSPACE_MAX_END_END_PFX_OFFSET               22
#define HIPCIEC_EPF_CFGSPACE_END_END_PFX_SUP_LEN                  1
#define HIPCIEC_EPF_CFGSPACE_END_END_PFX_SUP_OFFSET               21
#define HIPCIEC_EPF_CFGSPACE_EXT_FMT_SUP_LEN                      1
#define HIPCIEC_EPF_CFGSPACE_EXT_FMT_SUP_OFFSET                   20
#define HIPCIEC_EPF_CFGSPACE_OBFF_SUP_LEN                         2
#define HIPCIEC_EPF_CFGSPACE_OBFF_SUP_OFFSET                      18
#define HIPCIEC_EPF_CFGSPACE_SUP_10BIT_REQ_TAG_LEN                1
#define HIPCIEC_EPF_CFGSPACE_SUP_10BIT_REQ_TAG_OFFSET             17
#define HIPCIEC_EPF_CFGSPACE_SUP_10BIT_CPL_TAG_LEN                1
#define HIPCIEC_EPF_CFGSPACE_SUP_10BIT_CPL_TAG_OFFSET             16
#define HIPCIEC_EPF_CFGSPACE_LN_SYS_CLS_LEN                       2
#define HIPCIEC_EPF_CFGSPACE_LN_SYS_CLS_OFFSET                    14
#define HIPCIEC_EPF_CFGSPACE_TPH_CPL_SUP_LEN                      2
#define HIPCIEC_EPF_CFGSPACE_TPH_CPL_SUP_OFFSET                   12
#define HIPCIEC_EPF_CFGSPACE_LTR_MECH_SUP_LEN                     1
#define HIPCIEC_EPF_CFGSPACE_LTR_MECH_SUP_OFFSET                  11
#define HIPCIEC_EPF_CFGSPACE_NO_ROEN_PRPR_PASS_LEN                1
#define HIPCIEC_EPF_CFGSPACE_NO_ROEN_PRPR_PASS_OFFSET             10
#define HIPCIEC_EPF_CFGSPACE_CAS_128BIT_CPL_SUP_LEN               1
#define HIPCIEC_EPF_CFGSPACE_CAS_128BIT_CPL_SUP_OFFSET            9
#define HIPCIEC_EPF_CFGSPACE_ATOMIC_64BIT_CPL_SUP_LEN             1
#define HIPCIEC_EPF_CFGSPACE_ATOMIC_64BIT_CPL_SUP_OFFSET          8
#define HIPCIEC_EPF_CFGSPACE_ATOMIC_32BIT_CPL_SUP_LEN             1
#define HIPCIEC_EPF_CFGSPACE_ATOMIC_32BIT_CPL_SUP_OFFSET          7
#define HIPCIEC_EPF_CFGSPACE_ATOMICOP_ROUTE_SUP_LEN               1
#define HIPCIEC_EPF_CFGSPACE_ATOMICOP_ROUTE_SUP_OFFSET            6
#define HIPCIEC_EPF_CFGSPACE_ARI_FWD_SUP_LEN                      1
#define HIPCIEC_EPF_CFGSPACE_ARI_FWD_SUP_OFFSET                   5
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEOUT_DISABLE_SUP_LEN          1
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEOUT_DISABLE_SUP_OFFSET       4
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEOUT_RANGE_LEN                4
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEOUT_RANGE_OFFSET             0

#define HIPCIEC_EPF_CFGSPACE_END_END_PFX_BLK_LEN             1
#define HIPCIEC_EPF_CFGSPACE_END_END_PFX_BLK_OFFSET          15
#define HIPCIEC_EPF_CFGSPACE_OBFF_EN_LEN                     2
#define HIPCIEC_EPF_CFGSPACE_OBFF_EN_OFFSET                  13
#define HIPCIEC_EPF_CFGSPACE_EN_10BIT_REQ_TAG_LEN            1
#define HIPCIEC_EPF_CFGSPACE_EN_10BIT_REQ_TAG_OFFSET         12
#define HIPCIEC_EPF_CFGSPACE_EMERGENCY_PWR_REDUCE_REQ_LEN    1
#define HIPCIEC_EPF_CFGSPACE_EMERGENCY_PWR_REDUCE_REQ_OFFSET 11
#define HIPCIEC_EPF_CFGSPACE_LTR_MECH_EN_LEN                 1
#define HIPCIEC_EPF_CFGSPACE_LTR_MECH_EN_OFFSET              10
#define HIPCIEC_EPF_CFGSPACE_IDO_CPL_EN_LEN                  1
#define HIPCIEC_EPF_CFGSPACE_IDO_CPL_EN_OFFSET               9
#define HIPCIEC_EPF_CFGSPACE_IDO_REQ_EN_LEN                  1
#define HIPCIEC_EPF_CFGSPACE_IDO_REQ_EN_OFFSET               8
#define HIPCIEC_EPF_CFGSPACE_ATOMICOP_EGRESS_BLK_LEN         1
#define HIPCIEC_EPF_CFGSPACE_ATOMICOP_EGRESS_BLK_OFFSET      7
#define HIPCIEC_EPF_CFGSPACE_ATOMICOP_REQ_EN_LEN             1
#define HIPCIEC_EPF_CFGSPACE_ATOMICOP_REQ_EN_OFFSET          6
#define HIPCIEC_EPF_CFGSPACE_ARI_FWD_EN_LEN                  1
#define HIPCIEC_EPF_CFGSPACE_ARI_FWD_EN_OFFSET               5
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEOUT_DIS_LEN             1
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEOUT_DIS_OFFSET          4
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEOUT_VALUE_LEN           4
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEOUT_VALUE_OFFSET        0

#define HIPCIEC_EPF_CFGSPACE_DRS_SUP_LEN                         1
#define HIPCIEC_EPF_CFGSPACE_DRS_SUP_OFFSET                      31
#define HIPCIEC_EPF_CFGSPACE_RETIMER2_PRESENCE_DETECT_SUP_LEN    1
#define HIPCIEC_EPF_CFGSPACE_RETIMER2_PRESENCE_DETECT_SUP_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RETIMER_PRESENCE_DETECT_SUP_LEN     1
#define HIPCIEC_EPF_CFGSPACE_RETIMER_PRESENCE_DETECT_SUP_OFFSET  23
#define HIPCIEC_EPF_CFGSPACE_CFG_RX_LOWER_SKP_CAP_LEN            7
#define HIPCIEC_EPF_CFGSPACE_CFG_RX_LOWER_SKP_CAP_OFFSET         16
#define HIPCIEC_EPF_CFGSPACE_CFG_TX_LOWER_SKP_CAP_LEN            7
#define HIPCIEC_EPF_CFGSPACE_CFG_TX_LOWER_SKP_CAP_OFFSET         9
#define HIPCIEC_EPF_CFGSPACE_CROSS_LINK_SUP_LEN                  1
#define HIPCIEC_EPF_CFGSPACE_CROSS_LINK_SUP_OFFSET               8
#define HIPCIEC_EPF_CFGSPACE_LINK_SPEED_SUP_LEN                  7
#define HIPCIEC_EPF_CFGSPACE_LINK_SPEED_SUP_OFFSET               1

#define HIPCIEC_EPF_CFGSPACE_DRS_MSG_RECVED_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_DRS_MSG_RECVED_OFFSET                31
#define HIPCIEC_EPF_CFGSPACE_DOWNSTREAM_COMPONENT_PRESENCE_LEN    3
#define HIPCIEC_EPF_CFGSPACE_DOWNSTREAM_COMPONENT_PRESENCE_OFFSET 28
#define HIPCIEC_EPF_CFGSPACE_CROSSLINK_RESOLUTION_LEN             2
#define HIPCIEC_EPF_CFGSPACE_CROSSLINK_RESOLUTION_OFFSET          24
#define HIPCIEC_EPF_CFGSPACE_RETIMER2_PRESENCE_DETECT_LEN         1
#define HIPCIEC_EPF_CFGSPACE_RETIMER2_PRESENCE_DETECT_OFFSET      23
#define HIPCIEC_EPF_CFGSPACE_RETIMER_PRESENCE_DETECT_LEN          1
#define HIPCIEC_EPF_CFGSPACE_RETIMER_PRESENCE_DETECT_OFFSET       22
#define HIPCIEC_EPF_CFGSPACE_LINK_8G_EQ_REQ_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_LINK_8G_EQ_REQ_OFFSET                21
#define HIPCIEC_EPF_CFGSPACE_EQ_8G_PHASE3_SUCCESS_LEN             1
#define HIPCIEC_EPF_CFGSPACE_EQ_8G_PHASE3_SUCCESS_OFFSET          20
#define HIPCIEC_EPF_CFGSPACE_EQ_8G_PHASE2_SUCCESS_LEN             1
#define HIPCIEC_EPF_CFGSPACE_EQ_8G_PHASE2_SUCCESS_OFFSET          19
#define HIPCIEC_EPF_CFGSPACE_EQ_8G_PHASE1_SUCCESS_LEN             1
#define HIPCIEC_EPF_CFGSPACE_EQ_8G_PHASE1_SUCCESS_OFFSET          18
#define HIPCIEC_EPF_CFGSPACE_EQ_8G_COMPLETE_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_EQ_8G_COMPLETE_OFFSET                17
#define HIPCIEC_EPF_CFGSPACE_CUR_DEEMP_LEVEL_LEN                  1
#define HIPCIEC_EPF_CFGSPACE_CUR_DEEMP_LEVEL_OFFSET               16
#define HIPCIEC_EPF_CFGSPACE_COMPLIANCE_PRESET_DEEMP_LEN          4
#define HIPCIEC_EPF_CFGSPACE_COMPLIANCE_PRESET_DEEMP_OFFSET       12
#define HIPCIEC_EPF_CFGSPACE_COMPLIANCE_SOS_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_COMPLIANCE_SOS_OFFSET                11
#define HIPCIEC_EPF_CFGSPACE_ENTER_MOD_COMPLIANCE_LEN             1
#define HIPCIEC_EPF_CFGSPACE_ENTER_MOD_COMPLIANCE_OFFSET          10
#define HIPCIEC_EPF_CFGSPACE_TRANSMIT_MARGIN_LEN                  3
#define HIPCIEC_EPF_CFGSPACE_TRANSMIT_MARGIN_OFFSET               7
#define HIPCIEC_EPF_CFGSPACE_SELECTABLE_DE_EMPHASIS_LEN           1
#define HIPCIEC_EPF_CFGSPACE_SELECTABLE_DE_EMPHASIS_OFFSET        6
#define HIPCIEC_EPF_CFGSPACE_HW_AUTO_SPEED_DIS_LEN                1
#define HIPCIEC_EPF_CFGSPACE_HW_AUTO_SPEED_DIS_OFFSET             5
#define HIPCIEC_EPF_CFGSPACE_ENTER_COMPLIANCE_LEN                 1
#define HIPCIEC_EPF_CFGSPACE_ENTER_COMPLIANCE_OFFSET              4
#define HIPCIEC_EPF_CFGSPACE_TARGET_LINK_SPEED_LEN                4
#define HIPCIEC_EPF_CFGSPACE_TARGET_LINK_SPEED_OFFSET             0

#define HIPCIEC_EPF_CFGSPACE_SLOT_CAP_2_LEN    32
#define HIPCIEC_EPF_CFGSPACE_SLOT_CAP_2_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_SLOT_CTRL_2_LEN    32
#define HIPCIEC_EPF_CFGSPACE_SLOT_CTRL_2_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_MSI_PVM_ENABLE_LEN         1
#define HIPCIEC_EPF_CFGSPACE_MSI_PVM_ENABLE_OFFSET      24
#define HIPCIEC_EPF_CFGSPACE_MSI_64BIT_ENABLE_LEN       1
#define HIPCIEC_EPF_CFGSPACE_MSI_64BIT_ENABLE_OFFSET    23
#define HIPCIEC_EPF_CFGSPACE_MSI_MULT_MSG_ENABLE_LEN    3
#define HIPCIEC_EPF_CFGSPACE_MSI_MULT_MSG_ENABLE_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_MSI_MULT_MSG_CAP_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MSI_MULT_MSG_CAP_OFFSET    17
#define HIPCIEC_EPF_CFGSPACE_MSI_ENABLE_LEN             1
#define HIPCIEC_EPF_CFGSPACE_MSI_ENABLE_OFFSET          16
#define HIPCIEC_EPF_CFGSPACE_MSI_NEXT_CAP_ADDR_LEN      8
#define HIPCIEC_EPF_CFGSPACE_MSI_NEXT_CAP_ADDR_OFFSET   8
#define HIPCIEC_EPF_CFGSPACE_MSI_CAP_ID_LEN             8
#define HIPCIEC_EPF_CFGSPACE_MSI_CAP_ID_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MSI_LADDR_LEN    30
#define HIPCIEC_EPF_CFGSPACE_MSI_LADDR_OFFSET 2

#define HIPCIEC_EPF_CFGSPACE_MSI_UADDR_LEN    32
#define HIPCIEC_EPF_CFGSPACE_MSI_UADDR_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_MSI_DATA_LEN    16
#define HIPCIEC_EPF_CFGSPACE_MSI_DATA_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_MSI_MASK_LEN    32
#define HIPCIEC_EPF_CFGSPACE_MSI_MASK_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_MSI_PENDING_LEN    32
#define HIPCIEC_EPF_CFGSPACE_MSI_PENDING_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_MSIX_ENABLE_LEN           1
#define HIPCIEC_EPF_CFGSPACE_MSIX_ENABLE_OFFSET        31
#define HIPCIEC_EPF_CFGSPACE_MSIX_FUNC_MASK_LEN        1
#define HIPCIEC_EPF_CFGSPACE_MSIX_FUNC_MASK_OFFSET     30
#define HIPCIEC_EPF_CFGSPACE_MSIX_TABLE_SIZE_LEN       11
#define HIPCIEC_EPF_CFGSPACE_MSIX_TABLE_SIZE_OFFSET    16
#define HIPCIEC_EPF_CFGSPACE_MSIX_NEXT_CAP_ADDR_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MSIX_NEXT_CAP_ADDR_OFFSET 8
#define HIPCIEC_EPF_CFGSPACE_MSIX_CAP_ID_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MSIX_CAP_ID_OFFSET        0

#define HIPCIEC_EPF_CFGSPACE_MSIX_TABLE_OFFSET_LEN    29
#define HIPCIEC_EPF_CFGSPACE_MSIX_TABLE_OFFSET_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_MSIX_TABLE_BIR_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MSIX_TABLE_BIR_OFFSET    0

#define HIPCIEC_EPF_CFGSPACE_MSIX_PBA_OFFSET_LEN    29
#define HIPCIEC_EPF_CFGSPACE_MSIX_PBA_OFFSET_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_MSIX_PBA_BIR_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MSIX_PBA_BIR_OFFSET    0

#define HIPCIEC_EPF_CFGSPACE_PME_SUPPORT_LEN               5
#define HIPCIEC_EPF_CFGSPACE_PME_SUPPORT_OFFSET            27
#define HIPCIEC_EPF_CFGSPACE_D2_SUPPORT_LEN                1
#define HIPCIEC_EPF_CFGSPACE_D2_SUPPORT_OFFSET             26
#define HIPCIEC_EPF_CFGSPACE_D1_SUPPORT_LEN                1
#define HIPCIEC_EPF_CFGSPACE_D1_SUPPORT_OFFSET             25
#define HIPCIEC_EPF_CFGSPACE_AUX_CURRENT_LEN               3
#define HIPCIEC_EPF_CFGSPACE_AUX_CURRENT_OFFSET            22
#define HIPCIEC_EPF_CFGSPACE_DEVICE_SPEC_INI_LEN           1
#define HIPCIEC_EPF_CFGSPACE_DEVICE_SPEC_INI_OFFSET        21
#define HIPCIEC_EPF_CFGSPACE_IMMEDIATE_RN_RETURN_D0_LEN    1
#define HIPCIEC_EPF_CFGSPACE_IMMEDIATE_RN_RETURN_D0_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_PME_CLK_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_PME_CLK_OFFSET                19
#define HIPCIEC_EPF_CFGSPACE_PME_VESION_LEN                3
#define HIPCIEC_EPF_CFGSPACE_PME_VESION_OFFSET             16
#define HIPCIEC_EPF_CFGSPACE_PME_NEXT_PTR_LEN              8
#define HIPCIEC_EPF_CFGSPACE_PME_NEXT_PTR_OFFSET           8
#define HIPCIEC_EPF_CFGSPACE_PME_CAPABILITY_ID_LEN         8
#define HIPCIEC_EPF_CFGSPACE_PME_CAPABILITY_ID_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_PME_DATA_LEN         8
#define HIPCIEC_EPF_CFGSPACE_PME_DATA_OFFSET      24
#define HIPCIEC_EPF_CFGSPACE_BPCC_EN_LEN          1
#define HIPCIEC_EPF_CFGSPACE_BPCC_EN_OFFSET       23
#define HIPCIEC_EPF_CFGSPACE_B2_B3_N_LEN          1
#define HIPCIEC_EPF_CFGSPACE_B2_B3_N_OFFSET       22
#define HIPCIEC_EPF_CFGSPACE_PME_STATUS_LEN       1
#define HIPCIEC_EPF_CFGSPACE_PME_STATUS_OFFSET    15
#define HIPCIEC_EPF_CFGSPACE_DATA_SCALE_LEN       2
#define HIPCIEC_EPF_CFGSPACE_DATA_SCALE_OFFSET    13
#define HIPCIEC_EPF_CFGSPACE_DATA_SEL_LEN         4
#define HIPCIEC_EPF_CFGSPACE_DATA_SEL_OFFSET      9
#define HIPCIEC_EPF_CFGSPACE_PME_EN_LEN           1
#define HIPCIEC_EPF_CFGSPACE_PME_EN_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_NO_SOFT_RESET_LEN    1
#define HIPCIEC_EPF_CFGSPACE_NO_SOFT_RESET_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_PWR_STATUS_LEN       2
#define HIPCIEC_EPF_CFGSPACE_PWR_STATUS_OFFSET    0

#define HIPCIEC_EPF_CFGSPACE_AER_NEXT_CAP_ADDR_LEN       12
#define HIPCIEC_EPF_CFGSPACE_AER_NEXT_CAP_ADDR_OFFSET    20
#define HIPCIEC_EPF_CFGSPACE_AERCAPABILITYVERSION_LEN    4
#define HIPCIEC_EPF_CFGSPACE_AERCAPABILITYVERSION_OFFSET 16
#define HIPCIEC_EPF_CFGSPACE_AERCAPABILITYID_LEN         16
#define HIPCIEC_EPF_CFGSPACE_AERCAPABILITYID_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_POISONED_TLP_EGRESS_BLK_ERR_ST_LEN    1
#define HIPCIEC_EPF_CFGSPACE_POISONED_TLP_EGRESS_BLK_ERR_ST_OFFSET 26
#define HIPCIEC_EPF_CFGSPACE_TLP_PFX_BLK_ERR_ST_LEN                1
#define HIPCIEC_EPF_CFGSPACE_TLP_PFX_BLK_ERR_ST_OFFSET             25
#define HIPCIEC_EPF_CFGSPACE_ATOMICOP_EG_BLK_ST_LEN                1
#define HIPCIEC_EPF_CFGSPACE_ATOMICOP_EG_BLK_ST_OFFSET             24
#define HIPCIEC_EPF_CFGSPACE_MC_BLK_ST_LEN                         1
#define HIPCIEC_EPF_CFGSPACE_MC_BLK_ST_OFFSET                      23
#define HIPCIEC_EPF_CFGSPACE_UNCOR_INT_ERR_ST_LEN                  1
#define HIPCIEC_EPF_CFGSPACE_UNCOR_INT_ERR_ST_OFFSET               22
#define HIPCIEC_EPF_CFGSPACE_ACS_VIO_ST_LEN                        1
#define HIPCIEC_EPF_CFGSPACE_ACS_VIO_ST_OFFSET                     21
#define HIPCIEC_EPF_CFGSPACE_UR_ERR_ST_LEN                         1
#define HIPCIEC_EPF_CFGSPACE_UR_ERR_ST_OFFSET                      20
#define HIPCIEC_EPF_CFGSPACE_ECRC_ERR_ST_LEN                       1
#define HIPCIEC_EPF_CFGSPACE_ECRC_ERR_ST_OFFSET                    19
#define HIPCIEC_EPF_CFGSPACE_MAL_TLP_ST_LEN                        1
#define HIPCIEC_EPF_CFGSPACE_MAL_TLP_ST_OFFSET                     18
#define HIPCIEC_EPF_CFGSPACE_RCV_OVERFLOW_ST_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_RCV_OVERFLOW_ST_OFFSET                17
#define HIPCIEC_EPF_CFGSPACE_UNEXP_CPL_ST_LEN                      1
#define HIPCIEC_EPF_CFGSPACE_UNEXP_CPL_ST_OFFSET                   16
#define HIPCIEC_EPF_CFGSPACE_CPL_ABORT_ST_LEN                      1
#define HIPCIEC_EPF_CFGSPACE_CPL_ABORT_ST_OFFSET                   15
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEEOUT_ST_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEEOUT_ST_OFFSET                14
#define HIPCIEC_EPF_CFGSPACE_FC_PROTOCOL_ERR_ST_LEN                1
#define HIPCIEC_EPF_CFGSPACE_FC_PROTOCOL_ERR_ST_OFFSET             13
#define HIPCIEC_EPF_CFGSPACE_POISONED_TLP_ST_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_POISONED_TLP_ST_OFFSET                12
#define HIPCIEC_EPF_CFGSPACE_SUR_DOWN_ERR_ST_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_SUR_DOWN_ERR_ST_OFFSET                5
#define HIPCIEC_EPF_CFGSPACE_DL_PROTOCAL_ERR_ST_LEN                1
#define HIPCIEC_EPF_CFGSPACE_DL_PROTOCAL_ERR_ST_OFFSET             4
#define HIPCIEC_EPF_CFGSPACE_UNDEFINED_4_LEN                       1
#define HIPCIEC_EPF_CFGSPACE_UNDEFINED_4_OFFSET                    0

#define HIPCIEC_EPF_CFGSPACE_POISONED_TLP_EGRESS_BLK_ERR_MASK_LEN    1
#define HIPCIEC_EPF_CFGSPACE_POISONED_TLP_EGRESS_BLK_ERR_MASK_OFFSET 26
#define HIPCIEC_EPF_CFGSPACE_TLP_PFX_BLK_ERR_MASK_LEN                1
#define HIPCIEC_EPF_CFGSPACE_TLP_PFX_BLK_ERR_MASK_OFFSET             25
#define HIPCIEC_EPF_CFGSPACE_ATOMICOP_EG_BLK_MASK_LEN                1
#define HIPCIEC_EPF_CFGSPACE_ATOMICOP_EG_BLK_MASK_OFFSET             24
#define HIPCIEC_EPF_CFGSPACE_MC_BLK_MASK_LEN                         1
#define HIPCIEC_EPF_CFGSPACE_MC_BLK_MASK_OFFSET                      23
#define HIPCIEC_EPF_CFGSPACE_UNCOR_INT_ERR_MASK_LEN                  1
#define HIPCIEC_EPF_CFGSPACE_UNCOR_INT_ERR_MASK_OFFSET               22
#define HIPCIEC_EPF_CFGSPACE_ACS_VIO_MASK_LEN                        1
#define HIPCIEC_EPF_CFGSPACE_ACS_VIO_MASK_OFFSET                     21
#define HIPCIEC_EPF_CFGSPACE_UR_ERR_MASK_LEN                         1
#define HIPCIEC_EPF_CFGSPACE_UR_ERR_MASK_OFFSET                      20
#define HIPCIEC_EPF_CFGSPACE_ECRC_ERR_MASK_LEN                       1
#define HIPCIEC_EPF_CFGSPACE_ECRC_ERR_MASK_OFFSET                    19
#define HIPCIEC_EPF_CFGSPACE_MAL_TLP_MASK_LEN                        1
#define HIPCIEC_EPF_CFGSPACE_MAL_TLP_MASK_OFFSET                     18
#define HIPCIEC_EPF_CFGSPACE_RCV_OVERFLOW_MASK_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_RCV_OVERFLOW_MASK_OFFSET                17
#define HIPCIEC_EPF_CFGSPACE_UNEXP_CPL_MASK_LEN                      1
#define HIPCIEC_EPF_CFGSPACE_UNEXP_CPL_MASK_OFFSET                   16
#define HIPCIEC_EPF_CFGSPACE_CPL_ABORT_MASK_LEN                      1
#define HIPCIEC_EPF_CFGSPACE_CPL_ABORT_MASK_OFFSET                   15
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEEOUT_MASK_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEEOUT_MASK_OFFSET                14
#define HIPCIEC_EPF_CFGSPACE_FC_PROTOCOL_ERR_MASK_LEN                1
#define HIPCIEC_EPF_CFGSPACE_FC_PROTOCOL_ERR_MASK_OFFSET             13
#define HIPCIEC_EPF_CFGSPACE_POISONED_TLP_MASK_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_POISONED_TLP_MASK_OFFSET                12
#define HIPCIEC_EPF_CFGSPACE_SUR_DOWN_ERR_MASK_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_SUR_DOWN_ERR_MASK_OFFSET                5
#define HIPCIEC_EPF_CFGSPACE_DL_PROTOCAL_ERR_MASK_LEN                1
#define HIPCIEC_EPF_CFGSPACE_DL_PROTOCAL_ERR_MASK_OFFSET             4
#define HIPCIEC_EPF_CFGSPACE_UNDEFINED_8_LEN                         1
#define HIPCIEC_EPF_CFGSPACE_UNDEFINED_8_OFFSET                      0

#define HIPCIEC_EPF_CFGSPACE_POISONED_TLP_EGRESS_BLK_ERR_SER_LEN    1
#define HIPCIEC_EPF_CFGSPACE_POISONED_TLP_EGRESS_BLK_ERR_SER_OFFSET 26
#define HIPCIEC_EPF_CFGSPACE_TLP_PFX_BLK_ERR_SER_LEN                1
#define HIPCIEC_EPF_CFGSPACE_TLP_PFX_BLK_ERR_SER_OFFSET             25
#define HIPCIEC_EPF_CFGSPACE_ATOMICOP_EG_BLK_SER_LEN                1
#define HIPCIEC_EPF_CFGSPACE_ATOMICOP_EG_BLK_SER_OFFSET             24
#define HIPCIEC_EPF_CFGSPACE_MC_BLK_SER_LEN                         1
#define HIPCIEC_EPF_CFGSPACE_MC_BLK_SER_OFFSET                      23
#define HIPCIEC_EPF_CFGSPACE_UNCOR_INT_ERR_SER_LEN                  1
#define HIPCIEC_EPF_CFGSPACE_UNCOR_INT_ERR_SER_OFFSET               22
#define HIPCIEC_EPF_CFGSPACE_ACS_VIO_SER_LEN                        1
#define HIPCIEC_EPF_CFGSPACE_ACS_VIO_SER_OFFSET                     21
#define HIPCIEC_EPF_CFGSPACE_UR_ERR_SER_LEN                         1
#define HIPCIEC_EPF_CFGSPACE_UR_ERR_SER_OFFSET                      20
#define HIPCIEC_EPF_CFGSPACE_ECRC_ERR_SER_LEN                       1
#define HIPCIEC_EPF_CFGSPACE_ECRC_ERR_SER_OFFSET                    19
#define HIPCIEC_EPF_CFGSPACE_MAL_TLP_SER_LEN                        1
#define HIPCIEC_EPF_CFGSPACE_MAL_TLP_SER_OFFSET                     18
#define HIPCIEC_EPF_CFGSPACE_RCV_OVERFLOW_SER_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_RCV_OVERFLOW_SER_OFFSET                17
#define HIPCIEC_EPF_CFGSPACE_UNEXP_CPL_SER_LEN                      1
#define HIPCIEC_EPF_CFGSPACE_UNEXP_CPL_SER_OFFSET                   16
#define HIPCIEC_EPF_CFGSPACE_CPL_ABORT_SER_LEN                      1
#define HIPCIEC_EPF_CFGSPACE_CPL_ABORT_SER_OFFSET                   15
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEEOUT_SER_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_CPL_TIMEEOUT_SER_OFFSET                14
#define HIPCIEC_EPF_CFGSPACE_FC_PROTOCOL_ERR_SER_LEN                1
#define HIPCIEC_EPF_CFGSPACE_FC_PROTOCOL_ERR_SER_OFFSET             13
#define HIPCIEC_EPF_CFGSPACE_POISONED_TLP_SER_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_POISONED_TLP_SER_OFFSET                12
#define HIPCIEC_EPF_CFGSPACE_SUR_DOWN_ERR_SER_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_SUR_DOWN_ERR_SER_OFFSET                5
#define HIPCIEC_EPF_CFGSPACE_DL_PROTOCAL_ERR_SER_LEN                1
#define HIPCIEC_EPF_CFGSPACE_DL_PROTOCAL_ERR_SER_OFFSET             4
#define HIPCIEC_EPF_CFGSPACE_UNDEFINED_C_LEN                        1
#define HIPCIEC_EPF_CFGSPACE_UNDEFINED_C_OFFSET                     0

#define HIPCIEC_EPF_CFGSPACE_HEADER_LOG_OVERFLOW_ST_LEN       1
#define HIPCIEC_EPF_CFGSPACE_HEADER_LOG_OVERFLOW_ST_OFFSET    15
#define HIPCIEC_EPF_CFGSPACE_COR_INT_ERR_ST_LEN               1
#define HIPCIEC_EPF_CFGSPACE_COR_INT_ERR_ST_OFFSET            14
#define HIPCIEC_EPF_CFGSPACE_ADVISORY_NON_FATAL_ERR_ST_LEN    1
#define HIPCIEC_EPF_CFGSPACE_ADVISORY_NON_FATAL_ERR_ST_OFFSET 13
#define HIPCIEC_EPF_CFGSPACE_REPLY_TIMER_TIMOUT_ST_LEN        1
#define HIPCIEC_EPF_CFGSPACE_REPLY_TIMER_TIMOUT_ST_OFFSET     12
#define HIPCIEC_EPF_CFGSPACE_REPLY_NUM_ROLLOVER_ST_LEN        1
#define HIPCIEC_EPF_CFGSPACE_REPLY_NUM_ROLLOVER_ST_OFFSET     8
#define HIPCIEC_EPF_CFGSPACE_BAD_DLLP_ST_LEN                  1
#define HIPCIEC_EPF_CFGSPACE_BAD_DLLP_ST_OFFSET               7
#define HIPCIEC_EPF_CFGSPACE_BAD_TLP_ST_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_BAD_TLP_ST_OFFSET                6
#define HIPCIEC_EPF_CFGSPACE_RX_ERR_ST_LEN                    1
#define HIPCIEC_EPF_CFGSPACE_RX_ERR_ST_OFFSET                 0

#define HIPCIEC_EPF_CFGSPACE_HEADER_LOG_OVERFLOW_MASK_LEN       1
#define HIPCIEC_EPF_CFGSPACE_HEADER_LOG_OVERFLOW_MASK_OFFSET    15
#define HIPCIEC_EPF_CFGSPACE_COR_INT_ERR_MASK_LEN               1
#define HIPCIEC_EPF_CFGSPACE_COR_INT_ERR_MASK_OFFSET            14
#define HIPCIEC_EPF_CFGSPACE_ADVISORY_NON_FATAL_ERR_MASK_LEN    1
#define HIPCIEC_EPF_CFGSPACE_ADVISORY_NON_FATAL_ERR_MASK_OFFSET 13
#define HIPCIEC_EPF_CFGSPACE_REPLY_TIMER_TIMOUT_MASK_LEN        1
#define HIPCIEC_EPF_CFGSPACE_REPLY_TIMER_TIMOUT_MASK_OFFSET     12
#define HIPCIEC_EPF_CFGSPACE_REPLY_NUM_ROLLOVER_MASK_LEN        1
#define HIPCIEC_EPF_CFGSPACE_REPLY_NUM_ROLLOVER_MASK_OFFSET     8
#define HIPCIEC_EPF_CFGSPACE_BAD_DLLP_MASK_LEN                  1
#define HIPCIEC_EPF_CFGSPACE_BAD_DLLP_MASK_OFFSET               7
#define HIPCIEC_EPF_CFGSPACE_BAD_TLP_MASK_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_BAD_TLP_MASK_OFFSET                6
#define HIPCIEC_EPF_CFGSPACE_RX_ERR_MASK_LEN                    1
#define HIPCIEC_EPF_CFGSPACE_RX_ERR_MASK_OFFSET                 0

#define HIPCIEC_EPF_CFGSPACE_CMP_TIMEOUT_LOG_CAP_LEN     1
#define HIPCIEC_EPF_CFGSPACE_CMP_TIMEOUT_LOG_CAP_OFFSET  12
#define HIPCIEC_EPF_CFGSPACE_TLP_PREFIX_LOG_PRE_LEN      1
#define HIPCIEC_EPF_CFGSPACE_TLP_PREFIX_LOG_PRE_OFFSET   11
#define HIPCIEC_EPF_CFGSPACE_MULTI_HDR_REC_ENABLE_LEN    1
#define HIPCIEC_EPF_CFGSPACE_MULTI_HDR_REC_ENABLE_OFFSET 10
#define HIPCIEC_EPF_CFGSPACE_MULTI_HDR_REC_CAP_LEN       1
#define HIPCIEC_EPF_CFGSPACE_MULTI_HDR_REC_CAP_OFFSET    9
#define HIPCIEC_EPF_CFGSPACE_ECRC_CHECK_EN_LEN           1
#define HIPCIEC_EPF_CFGSPACE_ECRC_CHECK_EN_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_ECRC_CHECK_CAP_LEN          1
#define HIPCIEC_EPF_CFGSPACE_ECRC_CHECK_CAP_OFFSET       7
#define HIPCIEC_EPF_CFGSPACE_ECRC_GEN_EN_LEN             1
#define HIPCIEC_EPF_CFGSPACE_ECRC_GEN_EN_OFFSET          6
#define HIPCIEC_EPF_CFGSPACE_ECRC_GEN_CAP_LEN            1
#define HIPCIEC_EPF_CFGSPACE_ECRC_GEN_CAP_OFFSET         5
#define HIPCIEC_EPF_CFGSPACE_FIRST_ERR_PTR_LEN           5
#define HIPCIEC_EPF_CFGSPACE_FIRST_ERR_PTR_OFFSET        0

#define HIPCIEC_EPF_CFGSPACE_FIRST_HEADER_LOG_LEN    32
#define HIPCIEC_EPF_CFGSPACE_FIRST_HEADER_LOG_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_SECOND_HEADER_LOG_LEN    32
#define HIPCIEC_EPF_CFGSPACE_SECOND_HEADER_LOG_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_THIRD_HEADER_LOG_LEN    32
#define HIPCIEC_EPF_CFGSPACE_THIRD_HEADER_LOG_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_FOUR_HEADER_LOG_LEN    32
#define HIPCIEC_EPF_CFGSPACE_FOUR_HEADER_LOG_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_FATAL_ERR_EN_LEN        1
#define HIPCIEC_EPF_CFGSPACE_FATAL_ERR_EN_OFFSET     2
#define HIPCIEC_EPF_CFGSPACE_NON_FATAL_ERR_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_NON_FATAL_ERR_EN_OFFSET 1
#define HIPCIEC_EPF_CFGSPACE_COR_ERR_EN_LEN          1
#define HIPCIEC_EPF_CFGSPACE_COR_ERR_EN_OFFSET       0

#define HIPCIEC_EPF_CFGSPACE_AER_INT_NUMBER_LEN         5
#define HIPCIEC_EPF_CFGSPACE_AER_INT_NUMBER_OFFSET      27
#define HIPCIEC_EPF_CFGSPACE_FATAL_MSG_RCV_LEN          1
#define HIPCIEC_EPF_CFGSPACE_FATAL_MSG_RCV_OFFSET       6
#define HIPCIEC_EPF_CFGSPACE_NON_FATAL_MSG_RCV_LEN      1
#define HIPCIEC_EPF_CFGSPACE_NON_FATAL_MSG_RCV_OFFSET   5
#define HIPCIEC_EPF_CFGSPACE_FIRST_UNCOR_ERR_LEN        1
#define HIPCIEC_EPF_CFGSPACE_FIRST_UNCOR_ERR_OFFSET     4
#define HIPCIEC_EPF_CFGSPACE_MULTI_UNCOR_ERR_RCV_LEN    1
#define HIPCIEC_EPF_CFGSPACE_MULTI_UNCOR_ERR_RCV_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_UNCOR_ERR_RCV_LEN          1
#define HIPCIEC_EPF_CFGSPACE_UNCOR_ERR_RCV_OFFSET       2
#define HIPCIEC_EPF_CFGSPACE_MULTI_COR_ERR_RCV_LEN      1
#define HIPCIEC_EPF_CFGSPACE_MULTI_COR_ERR_RCV_OFFSET   1
#define HIPCIEC_EPF_CFGSPACE_CORE_ERR_RCV_LEN           1
#define HIPCIEC_EPF_CFGSPACE_CORE_ERR_RCV_OFFSET        0

#define HIPCIEC_EPF_CFGSPACE_ERR_NON_CIR_SOURCE_LEN    16
#define HIPCIEC_EPF_CFGSPACE_ERR_NON_CIR_SOURCE_OFFSET 16
#define HIPCIEC_EPF_CFGSPACE_ERR_COR_SOURCE_LEN        16
#define HIPCIEC_EPF_CFGSPACE_ERR_COR_SOURCE_OFFSET     0

#define HIPCIEC_EPF_CFGSPACE_FIRST_PREFIX_LOG_LEN    32
#define HIPCIEC_EPF_CFGSPACE_FIRST_PREFIX_LOG_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_SECOND_PREFIX_LOG_LEN    32
#define HIPCIEC_EPF_CFGSPACE_SECOND_PREFIX_LOG_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_THIRD_PREFIX_LOG_LEN    32
#define HIPCIEC_EPF_CFGSPACE_THIRD_PREFIX_LOG_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_FOUR_PREFIX_LOG_LEN    32
#define HIPCIEC_EPF_CFGSPACE_FOUR_PREFIX_LOG_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_ARI_NEXT_CAP_ADDR_LEN       12
#define HIPCIEC_EPF_CFGSPACE_ARI_NEXT_CAP_ADDR_OFFSET    20
#define HIPCIEC_EPF_CFGSPACE_ARICAPABILITYVERSION_LEN    4
#define HIPCIEC_EPF_CFGSPACE_ARICAPABILITYVERSION_OFFSET 16
#define HIPCIEC_EPF_CFGSPACE_ARICAPABILITYID_LEN         16
#define HIPCIEC_EPF_CFGSPACE_ARICAPABILITYID_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_FUNC_GROUP_LEN           3
#define HIPCIEC_EPF_CFGSPACE_FUNC_GROUP_OFFSET        20
#define HIPCIEC_EPF_CFGSPACE_ACS_FUNC_GRP_EN_LEN      1
#define HIPCIEC_EPF_CFGSPACE_ACS_FUNC_GRP_EN_OFFSET   17
#define HIPCIEC_EPF_CFGSPACE_MFVC_FUNC_GRP_EN_LEN     1
#define HIPCIEC_EPF_CFGSPACE_MFVC_FUNC_GRP_EN_OFFSET  16
#define HIPCIEC_EPF_CFGSPACE_NEXT_FUNC_NUM_LEN        8
#define HIPCIEC_EPF_CFGSPACE_NEXT_FUNC_NUM_OFFSET     8
#define HIPCIEC_EPF_CFGSPACE_ACS_FUNC_GRP_CAP_LEN     1
#define HIPCIEC_EPF_CFGSPACE_ACS_FUNC_GRP_CAP_OFFSET  1
#define HIPCIEC_EPF_CFGSPACE_MFVC_FUNC_GRP_CAP_LEN    1
#define HIPCIEC_EPF_CFGSPACE_MFVC_FUNC_GRP_CAP_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_SRIOV_NEXT_CAP_ADDR_LEN       12
#define HIPCIEC_EPF_CFGSPACE_SRIOV_NEXT_CAP_ADDR_OFFSET    20
#define HIPCIEC_EPF_CFGSPACE_SRIOVCAPABILITYVERSION_LEN    4
#define HIPCIEC_EPF_CFGSPACE_SRIOVCAPABILITYVERSION_OFFSET 16
#define HIPCIEC_EPF_CFGSPACE_SRIOVCAPABILITYID_LEN         16
#define HIPCIEC_EPF_CFGSPACE_SRIOVCAPABILITYID_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_VF_MIG_INT_LEN           11
#define HIPCIEC_EPF_CFGSPACE_VF_MIG_INT_OFFSET        21
#define HIPCIEC_EPF_CFGSPACE_VF_10BIT_TAG_SUP_LEN     1
#define HIPCIEC_EPF_CFGSPACE_VF_10BIT_TAG_SUP_OFFSET  2
#define HIPCIEC_EPF_CFGSPACE_ARI_CAP_HIER_PRES_LEN    1
#define HIPCIEC_EPF_CFGSPACE_ARI_CAP_HIER_PRES_OFFSET 1
#define HIPCIEC_EPF_CFGSPACE_VF_MIG_CAP_LEN           1
#define HIPCIEC_EPF_CFGSPACE_VF_MIG_CAP_OFFSET        0

#define HIPCIEC_EPF_CFGSPACE_VF_MIG_STATUS_LEN      1
#define HIPCIEC_EPF_CFGSPACE_VF_MIG_STATUS_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_VF_10BIT_TAG_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_VF_10BIT_TAG_EN_OFFSET 5
#define HIPCIEC_EPF_CFGSPACE_ARI_CAP_HIER_LEN       1
#define HIPCIEC_EPF_CFGSPACE_ARI_CAP_HIER_OFFSET    4
#define HIPCIEC_EPF_CFGSPACE_VF_MSE_LEN             1
#define HIPCIEC_EPF_CFGSPACE_VF_MSE_OFFSET          3
#define HIPCIEC_EPF_CFGSPACE_VF_MIG_INT_EN_LEN      1
#define HIPCIEC_EPF_CFGSPACE_VF_MIG_INT_EN_OFFSET   2
#define HIPCIEC_EPF_CFGSPACE_VF_MIG_EN_LEN          1
#define HIPCIEC_EPF_CFGSPACE_VF_MIG_EN_OFFSET       1
#define HIPCIEC_EPF_CFGSPACE_VF_EN_LEN              1
#define HIPCIEC_EPF_CFGSPACE_VF_EN_OFFSET           0

#define HIPCIEC_EPF_CFGSPACE_TOTL_VFS_LEN      16
#define HIPCIEC_EPF_CFGSPACE_TOTL_VFS_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_INITIAL_VF_LEN    16
#define HIPCIEC_EPF_CFGSPACE_INITIAL_VF_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_FUNC_DEPEN_LINK_LEN    8
#define HIPCIEC_EPF_CFGSPACE_FUNC_DEPEN_LINK_OFFSET 16
#define HIPCIEC_EPF_CFGSPACE_NUM_OF_VF_LEN          16
#define HIPCIEC_EPF_CFGSPACE_NUM_OF_VF_OFFSET       0

#define HIPCIEC_EPF_CFGSPACE_VF_STRIDE_LEN    16
#define HIPCIEC_EPF_CFGSPACE_VF_STRIDE_OFFSET 16
#define HIPCIEC_EPF_CFGSPACE_VF_OFFSET_LEN    16
#define HIPCIEC_EPF_CFGSPACE_VF_OFFSET_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_VF_DEVICE_ID_LEN    16
#define HIPCIEC_EPF_CFGSPACE_VF_DEVICE_ID_OFFSET 16

#define HIPCIEC_EPF_CFGSPACE_SUPPORT_PAGE_SIZE_LEN    32
#define HIPCIEC_EPF_CFGSPACE_SUPPORT_PAGE_SIZE_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_SYS_PAGE_SIZE_LEN    32
#define HIPCIEC_EPF_CFGSPACE_SYS_PAGE_SIZE_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_VF_BAR0_ADDR_LEN           28
#define HIPCIEC_EPF_CFGSPACE_VF_BAR0_ADDR_OFFSET        4
#define HIPCIEC_EPF_CFGSPACE_VF_BAR0_PREFETCH_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_VF_BAR0_PREFETCH_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_VF_BAR0_WIDTH_LEN          1
#define HIPCIEC_EPF_CFGSPACE_VF_BAR0_WIDTH_OFFSET       2
#define HIPCIEC_EPF_CFGSPACE_VF_BAR0_RESERVED_LEN       2
#define HIPCIEC_EPF_CFGSPACE_VF_BAR0_RESERVED_OFFSET    0

#define HIPCIEC_EPF_CFGSPACE_VF_BAR1_ADDR_LEN           28
#define HIPCIEC_EPF_CFGSPACE_VF_BAR1_ADDR_OFFSET        4
#define HIPCIEC_EPF_CFGSPACE_VF_BAR1_PREFETCH_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_VF_BAR1_PREFETCH_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_VF_BAR1_RESERVED_LEN       3
#define HIPCIEC_EPF_CFGSPACE_VF_BAR1_RESERVED_OFFSET    0

#define HIPCIEC_EPF_CFGSPACE_VF_BAR2_ADDR_LEN           28
#define HIPCIEC_EPF_CFGSPACE_VF_BAR2_ADDR_OFFSET        4
#define HIPCIEC_EPF_CFGSPACE_VF_BAR2_PREFETCH_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_VF_BAR2_PREFETCH_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_VF_BAR2_WIDTH_LEN          1
#define HIPCIEC_EPF_CFGSPACE_VF_BAR2_WIDTH_OFFSET       2
#define HIPCIEC_EPF_CFGSPACE_VF_BAR2_RESERVED_LEN       2
#define HIPCIEC_EPF_CFGSPACE_VF_BAR2_RESERVED_OFFSET    0

#define HIPCIEC_EPF_CFGSPACE_VF_BAR3_ADDR_LEN           28
#define HIPCIEC_EPF_CFGSPACE_VF_BAR3_ADDR_OFFSET        4
#define HIPCIEC_EPF_CFGSPACE_VF_BAR3_PREFETCH_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_VF_BAR3_PREFETCH_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_VF_BAR3_RESERVED_LEN       3
#define HIPCIEC_EPF_CFGSPACE_VF_BAR3_RESERVED_OFFSET    0

#define HIPCIEC_EPF_CFGSPACE_VF_BAR4_ADDR_LEN           28
#define HIPCIEC_EPF_CFGSPACE_VF_BAR4_ADDR_OFFSET        4
#define HIPCIEC_EPF_CFGSPACE_VF_BAR4_PREFETCH_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_VF_BAR4_PREFETCH_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_VF_BAR4_WIDTH_LEN          1
#define HIPCIEC_EPF_CFGSPACE_VF_BAR4_WIDTH_OFFSET       2
#define HIPCIEC_EPF_CFGSPACE_VF_BAR4_RESERVED_LEN       2
#define HIPCIEC_EPF_CFGSPACE_VF_BAR4_RESERVED_OFFSET    0

#define HIPCIEC_EPF_CFGSPACE_VF_BAR5_ADDR_LEN           28
#define HIPCIEC_EPF_CFGSPACE_VF_BAR5_ADDR_OFFSET        4
#define HIPCIEC_EPF_CFGSPACE_VF_BAR5_PREFETCH_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_VF_BAR5_PREFETCH_EN_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_VF_BAR5_RESERVED_LEN       3
#define HIPCIEC_EPF_CFGSPACE_VF_BAR5_RESERVED_OFFSET    0

#define HIPCIEC_EPF_CFGSPACE_VF_MIG_STATE_OFFSET_LEN    29
#define HIPCIEC_EPF_CFGSPACE_VF_MIG_STATE_OFFSET_OFFSET 3
#define HIPCIEC_EPF_CFGSPACE_VF_MIG_STATE_BIT_LEN       3
#define HIPCIEC_EPF_CFGSPACE_VF_MIG_STATE_BIT_OFFSET    0

#define HIPCIEC_EPF_CFGSPACE_ATS_NEXT_CAP_ADDR_LEN       12
#define HIPCIEC_EPF_CFGSPACE_ATS_NEXT_CAP_ADDR_OFFSET    20
#define HIPCIEC_EPF_CFGSPACE_ATSCAPABILITYVERSION_LEN    4
#define HIPCIEC_EPF_CFGSPACE_ATSCAPABILITYVERSION_OFFSET 16
#define HIPCIEC_EPF_CFGSPACE_ATSCAPABILITYID_LEN         16
#define HIPCIEC_EPF_CFGSPACE_ATSCAPABILITYID_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_ATS_EN_LEN                   1
#define HIPCIEC_EPF_CFGSPACE_ATS_EN_OFFSET                31
#define HIPCIEC_EPF_CFGSPACE_STU_LEN                      5
#define HIPCIEC_EPF_CFGSPACE_STU_OFFSET                   16
#define HIPCIEC_EPF_CFGSPACE_GLOBAL_INVALIDATE_SUP_LEN    1
#define HIPCIEC_EPF_CFGSPACE_GLOBAL_INVALIDATE_SUP_OFFSET 6
#define HIPCIEC_EPF_CFGSPACE_PAGE_ALIGNED_REQUEST_LEN     1
#define HIPCIEC_EPF_CFGSPACE_PAGE_ALIGNED_REQUEST_OFFSET  5
#define HIPCIEC_EPF_CFGSPACE_INVALID_Q_DEPTH_LEN          5
#define HIPCIEC_EPF_CFGSPACE_INVALID_Q_DEPTH_OFFSET       0

#define HIPCIEC_EPF_CFGSPACE_TPH_NEXT_CAP_OFFSET_LEN    12
#define HIPCIEC_EPF_CFGSPACE_TPH_NEXT_CAP_OFFSET_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_TPH_CAP_VERSION_LEN        4
#define HIPCIEC_EPF_CFGSPACE_TPH_CAP_VERSION_OFFSET     16
#define HIPCIEC_EPF_CFGSPACE_TPH_EXTEND_CAP_ID_LEN      16
#define HIPCIEC_EPF_CFGSPACE_TPH_EXTEND_CAP_ID_OFFSET   0

#define HIPCIEC_EPF_CFGSPACE_ST_TABLE_SIZE_LEN              11
#define HIPCIEC_EPF_CFGSPACE_ST_TABLE_SIZE_OFFSET           16
#define HIPCIEC_EPF_CFGSPACE_ST_TABLE_LOCATION_LEN          2
#define HIPCIEC_EPF_CFGSPACE_ST_TABLE_LOCATION_OFFSET       9
#define HIPCIEC_EPF_CFGSPACE_EXTEND_TPH_REQ_SUPPORT_LEN     1
#define HIPCIEC_EPF_CFGSPACE_EXTEND_TPH_REQ_SUPPORT_OFFSET  8
#define HIPCIEC_EPF_CFGSPACE_DEVICE_SPC_MODE_SUPPORT_LEN    1
#define HIPCIEC_EPF_CFGSPACE_DEVICE_SPC_MODE_SUPPORT_OFFSET 2
#define HIPCIEC_EPF_CFGSPACE_INT_VECTOR_MODE_SUPPORT_LEN    1
#define HIPCIEC_EPF_CFGSPACE_INT_VECTOR_MODE_SUPPORT_OFFSET 1
#define HIPCIEC_EPF_CFGSPACE_NO_ST_MODE_SUPPORT_LEN         1
#define HIPCIEC_EPF_CFGSPACE_NO_ST_MODE_SUPPORT_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_TPH_REQ_ENABLE_LEN    2
#define HIPCIEC_EPF_CFGSPACE_TPH_REQ_ENABLE_OFFSET 8
#define HIPCIEC_EPF_CFGSPACE_ST_MODE_SEL_LEN       3
#define HIPCIEC_EPF_CFGSPACE_ST_MODE_SEL_OFFSET    0

#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_NEXT_CAP_OFFSET_LEN    12
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_NEXT_CAP_OFFSET_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_CAP_VERSION_LEN        4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_CAP_VERSION_OFFSET     16
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_EXT_CAP_ID_LEN         16
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_EXT_CAP_ID_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_LOWER_SKP_EN_LEN               7
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_LOWER_SKP_EN_OFFSET            9
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_LINK_EQUALIZ_REQ_INT_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_LINK_EQUALIZ_REQ_INT_EN_OFFSET 1
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_PERFORM_EQUALIZ_LEN            1
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_PERFORM_EQUALIZ_OFFSET         0

#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_LANE_ERR_STAUS_LEN    16
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_LANE_ERR_STAUS_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN1_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN1_UP_RX_PRESET_HINT_OFFSET 28
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN1_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN1_UP_TX_PRESET_OFFSET      24
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN1_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN1_DP_RX_PRESET_HINT_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN1_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN1_DP_TX_PRESET_OFFSET      16
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN0_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN0_UP_RX_PRESET_HINT_OFFSET 12
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN0_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN0_UP_TX_PRESET_OFFSET      8
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN0_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN0_DP_RX_PRESET_HINT_OFFSET 4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN0_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN0_DP_TX_PRESET_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN3_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN3_UP_RX_PRESET_HINT_OFFSET 28
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN3_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN3_UP_TX_PRESET_OFFSET      24
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN3_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN3_DP_RX_PRESET_HINT_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN3_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN3_DP_TX_PRESET_OFFSET      16
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN2_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN2_UP_RX_PRESET_HINT_OFFSET 12
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN2_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN2_UP_TX_PRESET_OFFSET      8
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN2_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN2_DP_RX_PRESET_HINT_OFFSET 4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN2_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN2_DP_TX_PRESET_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN5_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN5_UP_RX_PRESET_HINT_OFFSET 28
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN5_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN5_UP_TX_PRESET_OFFSET      24
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN5_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN5_DP_RX_PRESET_HINT_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN5_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN5_DP_TX_PRESET_OFFSET      16
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN4_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN4_UP_RX_PRESET_HINT_OFFSET 12
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN4_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN4_UP_TX_PRESET_OFFSET      8
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN4_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN4_DP_RX_PRESET_HINT_OFFSET 4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN4_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN4_DP_TX_PRESET_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN7_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN7_UP_RX_PRESET_HINT_OFFSET 28
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN7_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN7_UP_TX_PRESET_OFFSET      24
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN7_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN7_DP_RX_PRESET_HINT_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN7_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN7_DP_TX_PRESET_OFFSET      16
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN6_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN6_UP_RX_PRESET_HINT_OFFSET 12
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN6_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN6_UP_TX_PRESET_OFFSET      8
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN6_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN6_DP_RX_PRESET_HINT_OFFSET 4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN6_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN6_DP_TX_PRESET_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN9_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN9_UP_RX_PRESET_HINT_OFFSET 28
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN9_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN9_UP_TX_PRESET_OFFSET      24
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN9_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN9_DP_RX_PRESET_HINT_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN9_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN9_DP_TX_PRESET_OFFSET      16
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN8_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN8_UP_RX_PRESET_HINT_OFFSET 12
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN8_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN8_UP_TX_PRESET_OFFSET      8
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN8_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN8_DP_RX_PRESET_HINT_OFFSET 4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN8_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN8_DP_TX_PRESET_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN11_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN11_UP_RX_PRESET_HINT_OFFSET 28
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN11_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN11_UP_TX_PRESET_OFFSET      24
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN11_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN11_DP_RX_PRESET_HINT_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN11_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN11_DP_TX_PRESET_OFFSET      16
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN10_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN10_UP_RX_PRESET_HINT_OFFSET 12
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN10_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN10_UP_TX_PRESET_OFFSET      8
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN10_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN10_DP_RX_PRESET_HINT_OFFSET 4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN10_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN10_DP_TX_PRESET_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN13_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN13_UP_RX_PRESET_HINT_OFFSET 28
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN13_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN13_UP_TX_PRESET_OFFSET      24
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN13_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN13_DP_RX_PRESET_HINT_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN13_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN13_DP_TX_PRESET_OFFSET      16
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN12_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN12_UP_RX_PRESET_HINT_OFFSET 12
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN12_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN12_UP_TX_PRESET_OFFSET      8
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN12_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN12_DP_RX_PRESET_HINT_OFFSET 4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN12_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN12_DP_TX_PRESET_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN15_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN15_UP_RX_PRESET_HINT_OFFSET 28
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN15_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN15_UP_TX_PRESET_OFFSET      24
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN15_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN15_DP_RX_PRESET_HINT_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN15_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN15_DP_TX_PRESET_OFFSET      16
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN14_UP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN14_UP_RX_PRESET_HINT_OFFSET 12
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN14_UP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN14_UP_TX_PRESET_OFFSET      8
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN14_DP_RX_PRESET_HINT_LEN    3
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN14_DP_RX_PRESET_HINT_OFFSET 4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN14_DP_TX_PRESET_LEN         4
#define HIPCIEC_EPF_CFGSPACE_SEC_PCIE_8G_LN14_DP_TX_PRESET_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_DSN_NEXT_CAP_OFFSET_LEN    12
#define HIPCIEC_EPF_CFGSPACE_DSN_NEXT_CAP_OFFSET_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_DSN_CAP_VERSION_LEN        4
#define HIPCIEC_EPF_CFGSPACE_DSN_CAP_VERSION_OFFSET     16
#define HIPCIEC_EPF_CFGSPACE_DSN_EXTEND_CAP_LEN         16
#define HIPCIEC_EPF_CFGSPACE_DSN_EXTEND_CAP_OFFSET      0

#define HIPCIEC_EPF_CFGSPACE_DSN_1ST_DW_LEN    32
#define HIPCIEC_EPF_CFGSPACE_DSN_1ST_DW_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_DSN_2ND_DW_LEN    32
#define HIPCIEC_EPF_CFGSPACE_DSN_2ND_DW_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_ACS_CAP_NEXT_CAP_ADDR_LEN    12
#define HIPCIEC_EPF_CFGSPACE_ACS_CAP_NEXT_CAP_ADDR_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_ACS_CAP_VERSION_LEN          4
#define HIPCIEC_EPF_CFGSPACE_ACS_CAP_VERSION_OFFSET       16
#define HIPCIEC_EPF_CFGSPACE_ACS_CAPID_LEN                16
#define HIPCIEC_EPF_CFGSPACE_ACS_CAPID_OFFSET             0

#define HIPCIEC_EPF_CFGSPACE_ACS_DIRECT_TX_P2P_EN_LEN       1
#define HIPCIEC_EPF_CFGSPACE_ACS_DIRECT_TX_P2P_EN_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_ACS_P2P_EGRESS_CTRL_EN_LEN     1
#define HIPCIEC_EPF_CFGSPACE_ACS_P2P_EGRESS_CTRL_EN_OFFSET  21
#define HIPCIEC_EPF_CFGSPACE_ACS_UP_FORWARD_EN_LEN          1
#define HIPCIEC_EPF_CFGSPACE_ACS_UP_FORWARD_EN_OFFSET       20
#define HIPCIEC_EPF_CFGSPACE_ACS_P2P_CPL_REDIRECT_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_ACS_P2P_CPL_REDIRECT_EN_OFFSET 19
#define HIPCIEC_EPF_CFGSPACE_ACS_P2P_REQ_REDIRECT_EN_LEN    1
#define HIPCIEC_EPF_CFGSPACE_ACS_P2P_REQ_REDIRECT_EN_OFFSET 18
#define HIPCIEC_EPF_CFGSPACE_ACS_TX_BLOCK_EN_LEN            1
#define HIPCIEC_EPF_CFGSPACE_ACS_TX_BLOCK_EN_OFFSET         17
#define HIPCIEC_EPF_CFGSPACE_ACS_SRC_VLD_EN_LEN             1
#define HIPCIEC_EPF_CFGSPACE_ACS_SRC_VLD_EN_OFFSET          16
#define HIPCIEC_EPF_CFGSPACE_ACS_CTRL_VEC_SIZE_LEN          8
#define HIPCIEC_EPF_CFGSPACE_ACS_CTRL_VEC_SIZE_OFFSET       8
#define HIPCIEC_EPF_CFGSPACE_ACS_DIRECT_TX_P2P_LEN          1
#define HIPCIEC_EPF_CFGSPACE_ACS_DIRECT_TX_P2P_OFFSET       6
#define HIPCIEC_EPF_CFGSPACE_ACS_P2P_EGRESS_CTRL_LEN        1
#define HIPCIEC_EPF_CFGSPACE_ACS_P2P_EGRESS_CTRL_OFFSET     5
#define HIPCIEC_EPF_CFGSPACE_ACS_UP_FORWARD_LEN             1
#define HIPCIEC_EPF_CFGSPACE_ACS_UP_FORWARD_OFFSET          4
#define HIPCIEC_EPF_CFGSPACE_ACS_P2P_CPL_REDIRECT_LEN       1
#define HIPCIEC_EPF_CFGSPACE_ACS_P2P_CPL_REDIRECT_OFFSET    3
#define HIPCIEC_EPF_CFGSPACE_ACS_P2P_REQ_REDIRECT_LEN       1
#define HIPCIEC_EPF_CFGSPACE_ACS_P2P_REQ_REDIRECT_OFFSET    2
#define HIPCIEC_EPF_CFGSPACE_ACS_TX_BLOCK_LEN               1
#define HIPCIEC_EPF_CFGSPACE_ACS_TX_BLOCK_OFFSET            1
#define HIPCIEC_EPF_CFGSPACE_ACS_SRC_VLD_LEN                1
#define HIPCIEC_EPF_CFGSPACE_ACS_SRC_VLD_OFFSET             0

#define HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAP_NEXT_CAP_ADDR_LEN    12
#define HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAP_NEXT_CAP_ADDR_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAP_VERSION_LEN          4
#define HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAP_VERSION_OFFSET       16
#define HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAPID_LEN                16
#define HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAPID_OFFSET             0

#define HIPCIEC_EPF_CFGSPACE_FEATURE_EXCHANGE_EN_LEN             1
#define HIPCIEC_EPF_CFGSPACE_FEATURE_EXCHANGE_EN_OFFSET          31
#define HIPCIEC_EPF_CFGSPACE_LOCAL_FUTURE_FEATURE_SUPPORT_LEN    22
#define HIPCIEC_EPF_CFGSPACE_LOCAL_FUTURE_FEATURE_SUPPORT_OFFSET 1
#define HIPCIEC_EPF_CFGSPACE_LOCAL_SCALE_FC_SUPPORT_LEN          1
#define HIPCIEC_EPF_CFGSPACE_LOCAL_SCALE_FC_SUPPORT_OFFSET       0

#define HIPCIEC_EPF_CFGSPACE_REMOTE_FEATURE_SUP_VLD_LEN           1
#define HIPCIEC_EPF_CFGSPACE_REMOTE_FEATURE_SUP_VLD_OFFSET        31
#define HIPCIEC_EPF_CFGSPACE_REMOTE_FUTURE_FEATURE_SUPPORT_LEN    22
#define HIPCIEC_EPF_CFGSPACE_REMOTE_FUTURE_FEATURE_SUPPORT_OFFSET 1
#define HIPCIEC_EPF_CFGSPACE_REMOTE_SCALE_FC_SUPPORT_LEN          1
#define HIPCIEC_EPF_CFGSPACE_REMOTE_SCALE_FC_SUPPORT_OFFSET       0

#define HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_NEXT_CAP_ADDR_LEN    12
#define HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_NEXT_CAP_ADDR_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_VERSION_LEN          4
#define HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_VERSION_OFFSET       16
#define HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAPID_LEN                16
#define HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAPID_OFFSET             0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_SOFT_READY_LEN         1
#define HIPCIEC_EPF_CFGSPACE_MARGIN_SOFT_READY_OFFSET      17
#define HIPCIEC_EPF_CFGSPACE_MARGIN_READY_LEN              1
#define HIPCIEC_EPF_CFGSPACE_MARGIN_READY_OFFSET           16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_USE_DRIVER_SOFT_LEN    1
#define HIPCIEC_EPF_CFGSPACE_MARGIN_USE_DRIVER_SOFT_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_0_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_0_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_0_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_0_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_0_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_0_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_0_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_0_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_0_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_0_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_0_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_0_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_0_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_0_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_0_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_0_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_0_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_0_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_0_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_0_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_1_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_1_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_1_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_1_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_1_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_1_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_1_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_1_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_1_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_1_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_1_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_1_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_1_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_1_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_1_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_1_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_1_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_1_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_1_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_1_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_2_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_2_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_2_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_2_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_2_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_2_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_2_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_2_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_2_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_2_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_2_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_2_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_2_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_2_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_2_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_2_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_2_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_2_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_2_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_2_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_3_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_3_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_3_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_3_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_3_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_3_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_3_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_3_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_3_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_3_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_3_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_3_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_3_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_3_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_3_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_3_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_3_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_3_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_3_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_3_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_4_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_4_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_4_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_4_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_4_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_4_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_4_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_4_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_4_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_4_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_4_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_4_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_4_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_4_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_4_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_4_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_4_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_4_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_4_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_4_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_5_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_5_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_5_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_5_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_5_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_5_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_5_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_5_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_5_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_5_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_5_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_5_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_5_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_5_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_5_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_5_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_5_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_5_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_5_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_5_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_6_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_6_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_6_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_6_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_6_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_6_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_6_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_6_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_6_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_6_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_6_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_6_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_6_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_6_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_6_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_6_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_6_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_6_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_6_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_6_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_7_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_7_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_7_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_7_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_7_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_7_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_7_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_7_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_7_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_7_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_7_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_7_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_7_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_7_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_7_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_7_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_7_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_7_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_7_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_7_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_8_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_8_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_8_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_8_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_8_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_8_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_8_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_8_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_8_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_8_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_8_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_8_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_8_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_8_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_8_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_8_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_8_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_8_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_8_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_8_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_9_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_9_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_9_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_9_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_9_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_9_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_9_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_9_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_9_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_9_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_9_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_9_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_9_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_9_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_9_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_9_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_9_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_9_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_9_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_9_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_10_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_10_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_10_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_10_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_10_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_10_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_10_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_10_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_10_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_10_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_10_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_10_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_10_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_10_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_10_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_10_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_10_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_10_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_10_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_10_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_11_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_11_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_11_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_11_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_11_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_11_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_11_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_11_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_11_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_11_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_11_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_11_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_11_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_11_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_11_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_11_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_11_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_11_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_11_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_11_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_12_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_12_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_12_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_12_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_12_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_12_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_12_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_12_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_12_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_12_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_12_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_12_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_12_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_12_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_12_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_12_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_12_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_12_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_12_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_12_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_13_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_13_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_13_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_13_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_13_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_13_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_13_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_13_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_13_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_13_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_13_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_13_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_13_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_13_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_13_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_13_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_13_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_13_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_13_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_13_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_14_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_14_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_14_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_14_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_14_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_14_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_14_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_14_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_14_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_14_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_14_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_14_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_14_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_14_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_14_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_14_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_14_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_14_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_14_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_14_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_15_LEN    8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_STATUS_15_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_15_LEN              1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT23_15_OFFSET           23
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_15_LEN       1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_STATUS_15_OFFSET    22
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_15_LEN       3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_STATUS_15_OFFSET    19
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_15_LEN      3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_STATUS_15_OFFSET   16
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_15_LEN           8
#define HIPCIEC_EPF_CFGSPACE_MARGIN_PAYLOAD_15_OFFSET        8
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_15_LEN               1
#define HIPCIEC_EPF_CFGSPACE_RSVDP_BIT7_15_OFFSET            7
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_15_LEN              1
#define HIPCIEC_EPF_CFGSPACE_USAGE_MODEL_15_OFFSET           6
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_15_LEN              3
#define HIPCIEC_EPF_CFGSPACE_MARGIN_TYPE_15_OFFSET           3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_15_LEN             3
#define HIPCIEC_EPF_CFGSPACE_RECEIVER_NUM_15_OFFSET          0

#define HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_NEXT_CAP_ADDR_LEN    12
#define HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_NEXT_CAP_ADDR_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_VERSION_LEN          4
#define HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_VERSION_OFFSET       16
#define HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAPID_LEN                16
#define HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAPID_OFFSET             0





#define HIPCIEC_EPF_CFGSPACE_GEN4_LINK_EQUALIZATION_REQ_LEN    1
#define HIPCIEC_EPF_CFGSPACE_GEN4_LINK_EQUALIZATION_REQ_OFFSET 4
#define HIPCIEC_EPF_CFGSPACE_GEN4_EQ_PHASE3_SUCC_LEN           1
#define HIPCIEC_EPF_CFGSPACE_GEN4_EQ_PHASE3_SUCC_OFFSET        3
#define HIPCIEC_EPF_CFGSPACE_GEN4_EQ_PHASE2_SUCC_LEN           1
#define HIPCIEC_EPF_CFGSPACE_GEN4_EQ_PHASE2_SUCC_OFFSET        2
#define HIPCIEC_EPF_CFGSPACE_GEN4_EQ_PHASE1_SUCC_LEN           1
#define HIPCIEC_EPF_CFGSPACE_GEN4_EQ_PHASE1_SUCC_OFFSET        1
#define HIPCIEC_EPF_CFGSPACE_GEN4_EQ_COMPLETE_LEN              1
#define HIPCIEC_EPF_CFGSPACE_GEN4_EQ_COMPLETE_OFFSET           0

#define HIPCIEC_EPF_CFGSPACE_LOCAL_DATA_PARITY_ERR_LEN    16
#define HIPCIEC_EPF_CFGSPACE_LOCAL_DATA_PARITY_ERR_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_RETIMER_DATA_PARITY_ERR_LEN    16
#define HIPCIEC_EPF_CFGSPACE_RETIMER_DATA_PARITY_ERR_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_RETIMER2_DATA_PARITY_ERR_LEN    16
#define HIPCIEC_EPF_CFGSPACE_RETIMER2_DATA_PARITY_ERR_OFFSET 0



#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE3_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE3_UP_TX_PRESET_OFFSET 28
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE3_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE3_DP_TX_PRESET_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE2_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE2_UP_TX_PRESET_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE2_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE2_DP_TX_PRESET_OFFSET 16
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE1_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE1_UP_TX_PRESET_OFFSET 12
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE1_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE1_DP_TX_PRESET_OFFSET 8
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE0_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE0_UP_TX_PRESET_OFFSET 4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE0_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE0_DP_TX_PRESET_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE7_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE7_UP_TX_PRESET_OFFSET 28
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE7_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE7_DP_TX_PRESET_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE6_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE6_UP_TX_PRESET_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE6_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE6_DP_TX_PRESET_OFFSET 16
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE5_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE5_UP_TX_PRESET_OFFSET 12
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE5_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE5_DP_TX_PRESET_OFFSET 8
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE4_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE4_UP_TX_PRESET_OFFSET 4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE4_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE4_DP_TX_PRESET_OFFSET 0

#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE11_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE11_UP_TX_PRESET_OFFSET 28
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE11_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE11_DP_TX_PRESET_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE10_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE10_UP_TX_PRESET_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE10_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE10_DP_TX_PRESET_OFFSET 16
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE9_UP_TX_PRESET_LEN     4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE9_UP_TX_PRESET_OFFSET  12
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE9_DP_TX_PRESET_LEN     4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE9_DP_TX_PRESET_OFFSET  8
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE8_UP_TX_PRESET_LEN     4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE8_UP_TX_PRESET_OFFSET  4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE8_DP_TX_PRESET_LEN     4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE8_DP_TX_PRESET_OFFSET  0

#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE15_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE15_UP_TX_PRESET_OFFSET 28
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE15_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE15_DP_TX_PRESET_OFFSET 24
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE14_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE14_UP_TX_PRESET_OFFSET 20
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE14_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE14_DP_TX_PRESET_OFFSET 16
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE13_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE13_UP_TX_PRESET_OFFSET 12
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE13_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE13_DP_TX_PRESET_OFFSET 8
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE12_UP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE12_UP_TX_PRESET_OFFSET 4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE12_DP_TX_PRESET_LEN    4
#define HIPCIEC_EPF_CFGSPACE_GEN4_LANE12_DP_TX_PRESET_OFFSET 0

#endif // __HIPCIEC_EPF_CFGSPACE_REG_OFFSET_FIELD_H__
